Due to limited on-chip caching, data-driven applications with large memory footprint encounter frequent cache misses Such applications suffer from recurring miss penalty when they re-reference recently evicted cache blocks To meet the worst-case performance requirements, Network-on-Chip (NoC) routers are provisioned with input port buffers However, recent studies reveal that these buffers remain underutilised except during network congestion Trace buffers are Design-for-Debug (DfD) hardware employed in NoC routers for post-silicon debug and validation Nevertheless, they become non-functional once a design goes into production and remain in the routers left unused In this article, we exploit the underutilised NoC router buffers and the unused trace buffers to store recently evicted cache blocks While these blocks are stored in the buffers, future re-reference to these blocks can be replied from the NoC router Such an opportunistic caching of evicted blocks in NoC routers significantly reduce the miss penalty Experimental analysis shows that the proposed architectures can achieve up to 21 percent (16 percent on average) reduction in miss penalty and 19 percent (14 percent on average) improvement in overall system performance While we have a negligible area and leakage power overhead of 258 and 394 percent, respectively, dynamic power reduces by 612 percent due to the improvement in performance

Opportunistic Caching in NoC: Exploring Ways to Reduce Miss Penalty

Switch Allocation (SA) holds a critical stage in Network-on-Chip (NoC) routers, its performance gets affected adversely due to Head-of-Line (HoL) blocking. In traditionally used Input-Queued Routers (IQR), packets are arranged in a particular order in each Virtual Channel (VC). This implementation is vulnerable to HoL blocking, as the switch allocator can allocate only those packets which are available at the head in a VC. In this paper, Swapped Buffer (SB) Router architecture is proposed to schedule packets in input buffers by using SB registers. The VCs are designed as SBs, this allows the packets stored in SB registers along with the head packet of VC to participate in SA. The concept of the SB register minimizes the conflicts in SA and thus reduces HoL blocking, therefore improves the performance of NoC. This paper proposes a priority mechanism to prioritize the non-head packets as compared to head packets in case of conflict between them. Two methods have been proposed in this paper, to enhance the performance of the NoC router. First, a VC allocation technique is proposed to optimize the order of packets in the input buffer. Next, SB-Router is combined with the Fill VC allocation technique to further enhance the performance of NoC routers. The performance of the proposed router is evaluated and the experimental results indicate that our design achieves latency improvement of 68.75% over (Time-Series) TS-Router for uniform traffic at the injection rate of 0.42 flits/cycle for a 64 node mesh network with moderate power consumption and area usage. The performance improvement in packet latency for traces from Princeton Application Repository for Shared-Memory Computers (PARSEC) has also been evaluated. With the achieved reduction in latency, the proposed method has the potential to serve high-speed operations while mapping different applications on multiple core architectures.

SB-Router: A Swapped Buffer Activated Low Latency Network-on-Chip Router

The era of data driven applications expose limited on-chip caching in modern Tiled Chip Multi-Processors (TCMPs). Some applications suffer from frequent last level cache (LLC) miss and travel off-chip to fetch data and instructions. Off-chip miss penalty is very expensive as it severely hampers application execution time. Modern Network-on-Chip (NoC) based TCMPs employ input buffered routers for scalable communication bandwidth. In this work, we exploit underutilised buffers of NoC routers to store recently evicted LLC blocks. While these blocks are locally stored, future data requests for such blocks are directly replied from the NoC router. Local reply from routers avoid off-chip travel and significantly reduces LLC miss penalty. To make sure that such storage of evicted LLC blocks does not create NoC congestion, we incorporate block forwarding and dropping using dynamic router buffer contention updates. We experimentally validate that our proposed optimisations significantly reduces LLC miss penalty and improves overall system performance. We achieve a maximum system speedup of up to 13% and an average system speedup of 7%.

Reducing Off-Chip Miss Penalty by Exploiting Underutilised On-Chip Router Buffers

Wasteful patterns that don't lead to fault dropping squander a tone of energy in the linear-feedback shift register and circuit under examination in a random research region. Random switching actions in the CUT and scan pathways between applications with two consecutive vectors are another significant cause of energy loss. This study proposes a unique built-in self-test (BIST) technique for scan-based circuits that might help save energy. Only the available vectors are produced in a fixed series thanks to a mapping logic that alters the LFSR's state transitions. As a consequence, and without reducing fault coverage, the time it takes to execute trials has decreased. Experiments on circuits demonstrated that during random testing, the linear feedback shift register saves a significant amount of power.

Power analyzer of linear feedback shift register techniques using built in self test

Current research in interfacing clusters within Hierarchical Networks-on-Chip (HNoC) as well as interfacing NoC-based systems adopts a centralized approach. In this approach, a specific Processing Element (PE) acts as a gateway between interfacing peripherals and the rest of NoC elements. This article evaluates this approach and show that it is not optimal for handling the inter-NoC communication. Routing inter-NoC traffic through a system to its gateway PE deteriorates the network performance. Results show that both the throughput and latency of the centralized approach degrade with the increase in the inter-NoC traffic bandwidth. To alleviate this, we propose a novel distributed approach, which separates the inter-NoC traffic from the intra-NoC one. Our approach relies on distributed buffers to allow PEs to efficiently communicate with the interfacing peripheral. We evaluate our approach against other interfacing ones using synthetic traffic as well as real benchmark applications. Our evaluation covers the whole system performance as well as its inter- and intra-NoC parts. Results prove that the proposed approach outperforms previous interfacing ones in terms of throughput and latency. The proposed approach significantly enhances the inter-NoC performance without any deterioration in the intra-NoC one. Considering the inter-NoC performance, we achieve a throughput that is close to the maximum possibly attainable one. Other approaches show major performance degradation, reaching as low as 10% of this maximum attainable throughput.

NoC 2 : An Efficient Interfacing Approach for Heavily-Communicating NoC-Based Systems

Ensuring the functional correctness of networks-on-chip (NoCs) can be particularly challenging, and communication-centric debug methodologies have been widely used by engineers to validate NoC functionality during post-silicon validation. Design-for-debug structures, such as trace buffers and monitors, are usually inserted in such systems-on-chip to enhance signal visibility. However, this debug hardware becomes underutilized once the chip goes into production. While the size and organization of the router buffers directly impact network throughput, these buffers also dominate the on-chip router area. We propose a scheme augmented virtual channel (AugVC) to reuse trace buffers to augment router buffers, with the objective of improving the overall network performance. The experimental results for a 64-node mesh network show that our proposed approach can reduce latency by up to 38.25% for transpose traffic compared to a baseline design with reduced buffer sizes. We also propose an extension, output port directed virtual channel (ODVC), that uses a modified virtual channel assignment strategy, on the basis of the designated output port of a network packet. This strategy reduces the average packet latency and area of the router by 45% and 32.4%, respectively.

Enhancing Network-on-Chip Performance by Reusing Trace Buffers

Cache memories are an indispensable component of many processor-based systems and contribute significantly to the overall area, power consumption, and delay. This leads to an important role played by modeling tools for estimating the area, power consumption, and access time of cache memories. However, existing modeling tools such as CACTI and its various extensions have been primarily designed using data from various projections. For the first time, we propose an entire flow for obtaining/calibrating the transistor characteristics from a commercial technology and use these characteristics within CACTI. We also improve the modeling approach to make them more fine-grained and follow recent manufacturing trends suitable for FinFET technology. Further, for the first time, we extend CACTI to support negative capacitance fin field effect transistor (NC-FinFET), an emerging technology depicting negative capacitance whose current and capacitive characteristics are very different compared to those of the FinFET. We use the proposed tool (FN-CACTI) to identify NC-FinFET-based caches to be significantly more energy-efficient than corresponding FinFET-based caches. We also study an application of FN-CACTI to determine optimal voltages corresponding to the lowest energy consumption for NC-FinFET and FinFET-based caches of various sizes.

Divya Praneetha Ravipati

Papers

Enhancing Network-on-Chip Performance by Reusing Trace Buffers

FN-CACTI: Advanced CACTI for FinFET and NC-FinFET Technologies

Performance and Energy Studies on NC-FinFET Cache-Based Systems With FN-McPAT