scispace - formally typeset
Journal ArticleDOI

FN-CACTI: Advanced CACTI for FinFET and NC-FinFET Technologies

TLDR
This work proposes an entire flow for obtaining/calibrating the transistor characteristics from a commercial technology and uses these characteristics within CACTI for the first time, and extends it to support negative capacitance fin field effect transistor (NC-FinFET), an emerging technology depictingnegative capacitance whose current and capacitive characteristics are very different compared to those of the FinFET.
Abstract
Cache memories are an indispensable component of many processor-based systems and contribute significantly to the overall area, power consumption, and delay. This leads to an important role played by modeling tools for estimating the area, power consumption, and access time of cache memories. However, existing modeling tools such as CACTI and its various extensions have been primarily designed using data from various projections. For the first time, we propose an entire flow for obtaining/calibrating the transistor characteristics from a commercial technology and use these characteristics within CACTI. We also improve the modeling approach to make them more fine-grained and follow recent manufacturing trends suitable for FinFET technology. Further, for the first time, we extend CACTI to support negative capacitance fin field effect transistor (NC-FinFET), an emerging technology depicting negative capacitance whose current and capacitive characteristics are very different compared to those of the FinFET. We use the proposed tool (FN-CACTI) to identify NC-FinFET-based caches to be significantly more energy-efficient than corresponding FinFET-based caches. We also study an application of FN-CACTI to determine optimal voltages corresponding to the lowest energy consumption for NC-FinFET and FinFET-based caches of various sizes.

read more

Content maybe subject to copyright    Report

Citations
More filters
Journal ArticleDOI

Optical and Electrical Memories for Analog Optical Computing

TL;DR: In this paper , the authors provide a forward-looking perspective on both optical and electrical memories coupled with integrated photonic hardware in the context of artificial intelligence and show that for programmed memories, the energy-latency product of photonic random access memory (PRAM) can be orders of magnitude lower compared to electronic SRAMs.
Proceedings ArticleDOI

AGNI: In-Situ, Iso-Latency Stochastic-to-Binary Number Conversion for In-DRAM Deep Learning

TL;DR: AGNI as mentioned in this paper proposes a new substrate for in-DRAM stochastic-to-binary number conversion called AGNI, which makes minor modifications in DRAM peripherals using pass transistors, capacitors, encoders, and charge pumps to enable in-situ binary conversion of input statistic operands of different sizes with iso latency.
Proceedings ArticleDOI

AGNI: In-Situ, Iso-Latency Stochastic-to-Binary Number Conversion for In-DRAM Deep Learning

TL;DR: AGNI as discussed by the authors proposes a new substrate for in-DRAM stochastic-to-binary number conversion called AGNI, which makes minor modifications in DRAM peripherals using pass transistors, capacitors, encoders, and charge pumps to enable in-situ binary conversion of input statistic operands of different sizes with iso latency.
References
More filters
Journal ArticleDOI

Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices

TL;DR: By replacing the standard insulator with a ferroelectric insulator of the right thickness it should be possible to implement a step-up voltage transformer that will amplify the gate voltage thus leading to values of S lower than 60 mV/decade and enabling low voltage/low power operation.
Journal ArticleDOI

CACTI: an enhanced cache access and cycle time model

TL;DR: In this paper, an analytical model for the access and cycle times of on-chip direct-mapped and set-associative caches is presented, where the inputs to the model are the cache size, block size, and associativity, as well as array organization and process parameters.
Proceedings ArticleDOI

Sniper: exploring the level of abstraction for scalable and accurate parallel multi-core simulation

TL;DR: Interval simulation provides a balance between detailed cycle-accurate simulation and one-IPC simulation, allowing long-running simulations to be modeled much faster than with detailed cycle, while still providing the detail necessary to observe core-uncore interactions across the entire system.
Journal ArticleDOI

ASAP7: A 7-nm finFET predictive process design kit

TL;DR: A high density, low-power standard cell architecture, developed using design/technology co-optimization (DTCO), as well as example SRAM cells are shown, and the PDK transistor electrical assumptions are explained, as are the FEOL and BEOL design rules.
Journal ArticleDOI

Unveiling the double-well energy landscape in a ferroelectric layer

TL;DR: A ferroelectric thin film that behaves as a single domain is found to exhibit both negative capacitance and the predicted double-well polarization–energy relationship, which could lead to fast adoption ofnegative capacitance effects in future products with markedly improved energy efficiency.