An all static CMOS ADPLL fabricated in 65 nm digital CMOS SOI technology has a fully programmable proportional-integral-differential (PID) loop filter and features a third order delta sigma modulator. The DCO is a three stage, static inverter based ring oscillator programmable in 768 frequency steps. The ADPLL lock range is 500 MHz to 8 GHz at 1.3 V and 25degC, and 90 MHz to 1.2 GHz at 0.5 V and 100degC. The IC dissipates 8 mW/GHz at 1.2 V and 1.6 mW/GHz at 0.5 V. The synthesized 4 GHz clock has a period jitter of 0.7 ps rms, and long term jitter of 6 ps rms. The phase noise under nominal operating conditions is 112 dBc/Hz measured at a 10 MHz offset from a 4 GHz center frequency. The total circuit area is 200 mum 150 mum.

A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI

The resolution of multi-bit linear TDC is closely related to process technology since the minimum resolvable time quantity is proportional to one-inverter delay [1]. For fine time resolution, vernier delay chains are frequently used [2,3]. Since the time resolution is determined by the difference between two inverter delays, a large number of inverter stages is required to cover a large detection range, resulting in long conversion time and high power consumption. Well-established data-conversion architectures have also been sought to achieve both large detection range and high resolution [4,5]. The two-step TDC was proposed to improve both the resolution and detectable range by amplifying the time residue after the coarse conversion for the fine conversion [4]. But, the previous time amplification schemes [4, 6] use metastability and suffer from small input range and gain uncertainties due to nonlinearity and PVT variations. This paper presents a power-efficient and wide dynamic range sub-exponent TDC. Based on a cascaded chain of 2× time amplifiers, the TDC generates the exponent-only information for the fractional time difference.

A 1 GHz ADPLL With a 1.25 ps Minimum-Resolution Sub-Exponent TDC in 0.18 $\mu$ m CMOS

An LC-VCO based phase-locked loop (PLL) frequency synthesizer which incorporates loop bandwidth tracking is described. In order to minimize loop bandwidth variations resulting from changes in the LC-VCO gain, the proposed PLL employs an averaging varactor based split-tuned LC-VCO and a servo loop which sets the charge-pump current to be inversely proportional to the square of the oscillation frequency. The combination of these techniques maintains a constant loop bandwidth over a wide range of operating frequencies. Fabricated in a 0.13 mum CMOS technology, the prototype chip measures less than plusmn4% variation in KVCOmiddotICP / N (equivalent to the variation in PLL loop bandwidth) for an operating frequency range of 3.1 to 3.9 GHz.

Method for a Constant Loop Bandwidth in LC-VCO PLL Frequency Synthesizers

A fast and high-precision all-digital automatic calibration circuit that is highly suited for ΔΣ fractional-N synthesizers is designed to achieve a constant loop bandwidth and fast lock time over an octave tuning range. A high-speed frequency-to-digital converter (FDC) measures VCO frequency on-chip with a sub-fREF frequency resolution of fREF/k in a time period of k·TREF. The on-chip detected VCO frequency is then used for calibrating the loop bandwidth and the VCO frequency. The loop bandwidth calibration circuit measures the VCO gain KVCO and uses it to precisely control the charge pump current, hence making the loop bandwidth constant. For the VCO frequency calibration, a minimum error code finding block significantly enhances the calibration accuracy by finding the truly closest code to the target frequency. Moreover, this method does not need to activate ΔΣ modulator to achieve sub- fREF calibration resolution, which makes this technique much accurate and faster than the conventional ones. A 1.9-3.8 GHz ΔΣ fractional-N synthesizer is implemented in 0.13 μm CMOS, demonstrating that the loop bandwidth calibration is completed in 1.1-6.0 μs with ±2% accuracy and the VCO frequency calibration is completed in 1.225-4.025 μs, all across the entire octave tuning range.

A 1.9–3.8 GHz $\Delta \Sigma$ Fractional-N PLL Frequency Synthesizer With Fast Auto-Calibration of Loop Bandwidth and VCO Frequency

This paper presents a novel all-digital CDR scheme in 90 nm CMOS. Two independently adjustable clock phases are generated from a delay line calibrated to 2 UI. One clock phase is placed in the middle of the eye to recover the data (“data clock”) and the other is swept across the delay line (“search clock”). As the search clock is swept, its samples are compared against the data samples to generate eye information. This information is used to determine the best phase for data recovery. After placing the search clock at this phase, search and data functions are traded between clocks and eye monitoring repeats. By trading functions, infinite delay range is realized using only a calibrated delay line, instead of a PLL or DLL. Since each clock generates its own alignment information, mismatches in clock distribution can be tolerated. The scheme's generalized sampling and retiming architecture is used in an efficient sharing technique that reduces the number of clocks required, saving power and area in high-density interconnect. The shared CDR is implemented using static CMOS logic in a 90 nm bulk process, occupying 0.15 mm2. It operates from 6 to 9 Gb/s, and consumes 2.5 mW/Gb/s of power at 6 Gb/s and 3.8 mW/Gb/s at 9 Gb/s.

A 3x9 Gb/s Shared, All-Digital CDR for High-Speed, High-Density I/O

This paper describes the design and implementation of an all-digital clock and data recovery circuit (ADCDR) for multigigabit/s operation. The proposed digitally-controlled oscillator (DCO) incorporating a supply-controlled ring oscillator with a digitally-controlled resistor (DCR) generates wide-frequency-range multiphase clocks with fine resolution. With an adaptive proportional gain controller (APGC) which continuously adjusts a proportional gain, the proposed ADCDR recovers data with a low-jitter clock and tracks large input jitter rapidly, resulting in enhanced jitter performance. A digital frequency-acquisition loop with a proportional control greatly reduces acquisition time. Fabricated in a 0.13-μm CMOS process with a 1.2-V supply, the ADCDR occupies 0.074 mm2 and operates from 1.0 Gb/s to 4.0 Gb/s with a bit error rate of less than 10-14. At a 3.0-Gb/s 231 - 1 PRBS, the measured jitter in the recovered clock is 3.59 psrms and 29.4 pspp, and the power consumption is 11.4 mW.

A 1.0–4.0-Gb/s All-Digital CDR With 1.0-ps Period Resolution DCO and Adaptive Proportional Gain Control

A 2.8Gb/s all-digital CDR uses a 10b glitch-free DCO which provides a 0.2 to 0.3% frequency tuning step to reduce the quantization effect. The CDR achieves 7.2psrms jitter at 2.5Gb/s and it operates from a 0.9 to 1.2V supply. The circuit occupies 300 times 430mum2 in a 0.13mum CMOS process and dissipates 13.2mW from a 1.2V supply when operating at 2.5Gb/s.

A 2.8Gb/s All-Digital CDR with a 10b Monotonic DCO

This paper describes the design and the implementation of a fully integrated 10 Gb Ethernet transceiver in a 0.13-/spl mu/m CMOS process using only a 1.2 V supply. A coarse control algorithm that combines a voltage range monitoring circuit with a frequency lock detector provides a robust operation against process, voltage, and temperature (PVT) variations for a VCO with a ring oscillator. With the use of a blind oversampling DPLL architecture, four channels of XAUI transceivers can share a single PLL, eliminating the clock synchronization problem between channels. Also, the total number of clock domains for the entire chip is reduced to three, making the integration of the XAUI with the 10G transceiver much simpler. The test chip consumes 898 mW from a 1.2 V supply.

A 1.2-V-only 900-mW 10 gb ethernet transceiver and XAUI interface with robust VCO tuning technique

A time-to-digital converter (TDC) includes a converter which receives a first signal and a second signal, delays the second signal in phases using a plurality of delay elements which are coupled in series, compares the delayed second signal with the first signal, and outputs a phase error of the second signal with respect to the first signal, a phase frequency detector which receives the first signal, and a third signal from one of the nodes in the plurality of delay elements, and outputs a phase difference between the first signal and the third signal, and a frequency detector which outputs a frequency error of the second signal with respect to the first signal as a digital code using an output signal of the phase frequency detector and the second signal.

Time-to-digital converter and all-digital phase-locked loop

A 10 Gb Ethernet transceiver chip integrated with 10 Gb/s serial and quad 3.125 Gb/s XAUI interfaces is implemented in 0.13 /spl mu/m CMOS and dissipates 898 mW from 1.2 V. A digital coarse control algorithm for VCOs reduced the VCO gains for noise immunity. A blind oversampling technique enabled synthesis of the XAUI interface.

Do-Hwan Oh

Papers

A 1.0–4.0-Gb/s All-Digital CDR With 1.0-ps Period Resolution DCO and Adaptive Proportional Gain Control

A 2.8Gb/s All-Digital CDR with a 10b Monotonic DCO

A 1.2-V-only 900-mW 10 gb ethernet transceiver and XAUI interface with robust VCO tuning technique

Time-to-digital converter and all-digital phase-locked loop

A fully integrated 0.13 /spl mu/m CMOS 10 Gb Ethernet transceiver with XAUI interface