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Design Of Analog Cmos Integrated Circuits

We might be at the turning point where research in microfluidics undertaken in academia and industrial research laboratories, and substantially sponsored by public grants, may provide a range of portable and networked diagnostic devices. In this Progress Report, an overview on microfluidic devices that may become the next generation of point-of-care (POC) diagnostics is provided. First, we describe gaps and opportunities in medical diagnostics and how microfluidics can address these gaps using the example of immunodiagnostics. Next, we conceptualize how different technologies are converging into working microfluidic POC diagnostics devices. Technologies are explained from the perspective of sample interaction with components of a device. Specifically, we detail materials, surface treatment, sample processing, microfluidic elements (such as valves, pumps, and mixers), receptors, and analytes in the light of various biosensing concepts. Finally, we discuss the integration of components into accurate and reliable devices.

Microfluidic Chips for Point‐of‐Care Immunodiagnostics

We propose a novel multiplier architecture with tunable error characteristics, that leverages a modified inaccurate 2x2 building block. Our inaccurate multipliers achieve an average power saving of 31.78% ? 45.4% over corresponding accurate multiplier designs, for an average error of 1.39%?3.32%. Using image filtering and JPEG compression as sample applications we show that our architecture can achieve 2X - 8X better Signal-Noise-Ratio (SNR) for the same power savings when compared to recent voltage over-scaling based power-error tradeoff methods. We project the multiplier power savings to bigger designs highlighting the fact that the benefits are strongly design dependent. We compare this circuit-centric approach to power quality tradeoffs with a pure software adaptation approach for a JPEG example. We also enhance the design to allow for correct operation of the multiplier using a residual adder, for non error resilient applications.

Trading Accuracy for Power with an Underdesigned Multiplier Architecture

A biosensor is an integrated receptor-transducer device, which can convert a biological response into an electrical signal The design and development of biosensors have taken a center stage for researchers or scientists in the recent decade owing to the wide range of biosensor applications, such as health care and disease diagnosis, environmental monitoring, water and food quality monitoring, and drug delivery The main challenges involved in the biosensor progress are (i) the efficient capturing of biorecognition signals and the transformation of these signals into electrochemical, electrical, optical, gravimetric, or acoustic signals (transduction process), (ii) enhancing transducer performance ie, increasing sensitivity, shorter response time, reproducibility, and low detection limits even to detect individual molecules, and (iii) miniaturization of the biosensing devices using micro-and nano-fabrication technologies Those challenges can be met through the integration of sensing technology with nanomaterials, which range from zero- to three-dimensional, possessing a high surface-to-volume ratio, good conductivities, shock-bearing abilities, and color tunability Nanomaterials (NMs) employed in the fabrication and nanobiosensors include nanoparticles (NPs) (high stability and high carrier capacity), nanowires (NWs) and nanorods (NRs) (capable of high detection sensitivity), carbon nanotubes (CNTs) (large surface area, high electrical and thermal conductivity), and quantum dots (QDs) (color tunability) Furthermore, these nanomaterials can themselves act as transduction elements This review summarizes the evolution of biosensors, the types of biosensors based on their receptors, transducers, and modern approaches employed in biosensors using nanomaterials such as NPs (eg, noble metal NPs and metal oxide NPs), NWs, NRs, CNTs, QDs, and dendrimers and their recent advancement in biosensing technology with the expansion of nanotechnology

A Review on Biosensors and Recent Development of Nanostructured Materials-Enabled Biosensors.

To evaluate the promise of potential computing technologies, this review examines a wide range of fundamental limits, such as to performance, power consumption, size and cost, from the device level to the system level. Computers have evolved at a remarkable rate, with improvements over the past fifty years roughly in line with Gordon Moore's prescient observation that the number of transistors in a dense integrated circuit would double approximately every two years. The rate of 'Moore scaling' is slowing down and other physical limits are looming, but new technologies such as carbon nanotubes, graphene and quantum computation are on the way. In this Review, Igor Markov takes a fresh look at the fundamental limits at various levels, from devices to complete systems, and compares loose and tight limits. Markov argues that the study of the limits of fundamental limits to computation can lead to new insights for emerging technologies. An indispensable part of our personal and working lives, computing has also become essential to industries and governments. Steady improvements in computer hardware have been supported by periodic doubling of transistor densities in integrated circuits over the past fifty years. Such Moore scaling now requires ever-increasing efforts, stimulating research in alternative hardware and stirring controversy. To help evaluate emerging technologies and increase our understanding of integrated-circuit scaling, here I review fundamental limits to computation in the areas of manufacturing, energy, physical space, design and verification effort, and algorithms. To outline what is achievable in principle and in practice, I recapitulate how some limits were circumvented, and compare loose and tight limits. Engineering difficulties encountered by emerging technologies may indicate yet unknown limits.

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Limits on fundamental limits to computation

We introduce and analyze the ground bounce due to power mode transition in power gating structures. To reduce the ground bounce, we propose novel power gating structures in which sleep transistors are turned on in a non-uniform stepwise manner. Our power gating structures reduce the magnitude of peak current and voltage glitches in the power distribution network as well as the minimum time required to stabilize power and ground. Experimental simulation results with PowerSpice fixtured in a package model demonstrate the effectiveness of the proposed power gate switching noise reduction techniques.

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Understanding and minimizing ground bounce during mode transition of power gating structures

A novel power gating structure is proposed for low-power, high-performance VLSI. This power gating structure supports an intermediate power saving mode as well as a traditional power cut-off mode. To evaluate our power gating structure, we design and fabricate three different macros in 0.13 /spl mu/m CMOS bulk technology. Our measurement results show that the additional intermediate power-mode allows us to cover various power-performance trade-off regimes, compared to conventional power gating structures.

Experimental measurement of a novel power gating structure with intermediate power saving mode

Dynamic logic families that rely on energy recovery to achieve low energy dissipation control the flow of data through gate cascades using multiphase clocks. Consequently, they typically use multiple clock generators and can exhibit increased energy consumption on their clock distribution networks. Moreover, they are not attractive for high-speed design due to their high complexity and clock skew management problems. In this paper, we present TSEL, the first energy-recovering (a.k.a. adiabatic) logic family that operates with a single-phase sinusoidal clocking scheme. We also present SCAL, a source-coupled variant of TSEL with improved supply voltage scalability and energy efficiency. Optimal performance under any operating conditions is achieved in SCAL using a tunable current source in each gate. TSEL and SCAL outperform previous adiabatic logic families in terms of energy efficiency and operating speed. In layout-based simulations with 0.5 /spl mu/m standard CMOS process parameters, 8-bit carry-lookahead adders (CLAs) in TSEL and SCAL function correctly for operating frequencies exceeding 200 MHz. In comparison with corresponding CLAs in alternative logic styles that operate at minimum supply voltages, CLAs designed in our single-phase adiabatic logic families are more energy efficient across a broad range of operating frequencies. Specifically, for clock rates ranging from 10 to 200 MHz, our andbit SCAL CLAs are 1.5 to 2.5 times more energy efficient than corresponding adders developed in PAL and 2N2P and 2.0 to 5.0 times less dissipative than their purely combinational or pipelined CMOS counterparts.

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True single-phase adiabatic circuitry

We present a low-complexity interface circuit for capacitive sensors that are integrated into sensor microsystems. To reduce hardware cost while keeping high resolution, a first-order delta-sigma modulator (DSM), which balances the charge from the capacitive difference between sense and reference capacitors with the charge from a fixed-quantity capacitor, is employed. A charge-mode digital-to-analog converter and a successive approximation register are utilized to automatically calibrate the zero point of the interface circuit, which may shift further than a dynamic range. A prototype circuit fabricated in a 0.35-μm CMOS process has an active area of 0.048 mm2. Its DSM operates at a sampling frequency of 1 MS/s with an oversampling ratio of 128. Experiments show that this circuit can read a capacitive difference from -0.5 to +0.5 pF with a 0.49-fF resolution. A capacitive offset that causes the zero point to shift can be canceled in the range from -2 to 2 pF with a 31.25-fF resolution. Measured power consumption was 1.44 mW at a 3.3-V supply.

A Delta–Sigma Interface Circuit for Capacitive Sensors With an Automatically Calibrated Zero Point

Most existing power gating structures provide only one power-saving mode. We propose a novel power gating structure that supports both a cutoff mode and an intermediate power-saving and data-retaining mode. Experiments with test structures fabricated in 0.13-mum CMOS bulk technology show that our power gating structure yields an expanded design space with more power-performance tradeoff alternatives.

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Suhwan Kim

Papers

Understanding and minimizing ground bounce during mode transition of power gating structures

Experimental measurement of a novel power gating structure with intermediate power saving mode

True single-phase adiabatic circuitry

A Delta–Sigma Interface Circuit for Capacitive Sensors With an Automatically Calibrated Zero Point

A Multi-Mode Power Gating Structure for Low-Voltage Deep-Submicron CMOS ICs