An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

FinFETs and Other Multi-Gate Transistors provides a comprehensive description of the physics, technology and circuit applications of multigate field-effect transistors (FETs). It explains the physics and properties of these devices, how they are fabricated and how circuit designers can use them to improve the performances of integrated circuits. The International Technology Roadmap for Semiconductors (ITRS) recognizes the importance of these devices and places them in the "Advanced non-classical CMOS devices" category. Of all the existing multigate devices, the FinFET is the most widely known. FinFETs and Other Multi-Gate Transistors is dedicated to the different facets of multigate FET technology and is written by leading experts in the field.

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FinFETs and Other Multi-Gate Transistors

Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

Power semiconductor devices and methods of manufacture

Atomically thin two-dimensional materials have emerged as promising candidates for flexible and transparent electronic applications. Here we show non-volatile memory devices, based on field-effect transistors with large hysteresis, consisting entirely of stacked two-dimensional materials. Graphene and molybdenum disulphide were employed as both channel and charge-trapping layers, whereas hexagonal boron nitride was used as a tunnel barrier. In these ultrathin heterostructured memory devices, the atomically thin molybdenum disulphide or graphene-trapping layer stores charge tunnelled through hexagonal boron nitride, serving as a floating gate to control the charge transport in the graphene or molybdenum disulphide channel. By varying the thicknesses of two-dimensional materials and modifying the stacking order, the hysteresis and conductance polarity of the field-effect transistor can be controlled. These devices show high mobility, high on/off current ratio, large memory window and stable retention, providing a promising route towards flexible and transparent memory devices utilizing atomically thin two-dimensional materials.

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Controlled charge trapping by molybdenum disulphide and graphene in ultrathin heterostructured memory devices

A method of fabricating a semiconductor structure including the steps of providing a silicon substrate (10) having a surface (12), forming on the surface (12) of the silicon substrate (10), by atomic layer deposition (ALD), a seed layer (20;20') characterised by a silicate material and forming, by atomic layer deposition (ALD) one or more layers of a high dielectric constant oxide (40) on the seed layer (20;20').

Method for fabricating a semiconductor structure including a metal oxide interface with silicon

A field effect transistor with a trench or groove gate having V-shaped walls is formed in a semiconductor substrate and a gate oxide is grown on the V-shaped walls to the surface of substrate and filled with a gate electrode material, such a polysilicon. Preferably, the bottom of the V-shaped walls are rounded before the trench is filled. Source/drain impurities either are diffused or implanted into the areas of the substrate on both sides of the surface oxide of the V-shaped gate. Contacts are made to the source, drain, and gate within field isolation to complete the structure. The resultant FET structure comprises a self aligned V-shaped gate having conventional source and drain surrounded by field isolation but with an effective channel length (Leff) of less than about one-half of the surface width of the gate. Preferably, the converging walls of the V-shaped gate end in a rounded concave bottom. Because of the V-shaped structure of the gate, the effective saturated length of the channel with drain voltage applied only extends from the edge of the source to just prior to the tip of the V-shaped structure in the interior of the semiconductor substrate. The drain side of the V-shaped structure becomes a depletion region due to the applied drain voltage. Due to this characteristic of such a structure, the surface width of the gate can be, for example, two or more times the distance of the desired channel length thereby permitting conventional lithography to be used to define the gate lengths much shorter than the lithographic limit.

Short channel self-aligned VMOS field effect transistor

High conductivity interconnection lines are formed of high conductivity material, such as copper, employing barrier layers impervious to the diffusion of copper atoms. Higher operating speeds are obtained with conductive interconnection lines, preferably copper interconnection lines, formed above the wire bonding layer.

High conductivity interconnection line

A combination vertical MOSFET and JFET device (18,22) is formed in a mesa (20,24) of semiconductor material. A top gate (44,68) of the device is formed by creating a preferably annular trench (36,58) that extends downwardly from the surface of the semiconductor layer, creating a thin gate insulator (41,62) on the bottom and sidewalls of this trench, and filling the trench with highly doped polysilicon. A buried gate region (28,50) is formed by implanting the semiconductor layer, prior to top gate formation, such that the buried gate region is laterally coextensive with the mesa. An upper boundary (29,54) of the buried gate region is spaced below the bottom of the trench and spaced from the semiconductor surface. Upon application of a suitable voltage, the buried gate region and the top gate region coact to invert the conductivity type of the channel region, permitting transistor operation between the source region and the drain region.

Trench-gated vertical combination JFET and MOSFET devices

A silicon oxide insulator (SOI) device includes an SOI layer supported on a silicon substrate. A body region is disposed on the SOI layer, and the body region is characterized by a first conductivity type. Source and drain regions are juxtaposed with the body region, with the source and drain regions being characterized by a second conductivity type. A transition region is disposed near the body region above the SOI layer, and the conductivity type of the transition region is established to be the first conductivity type for suppressing floating body effects in the body region and the second conductivity type for isolating the body region. An ohmic connector contacts the transition region and is connected to a drain power supply when the source and drain are doped with N-type dopants. On the other hand, the power supply is a source power supply when the source and drain are doped with P-type dopants. SOI bipolar transistors, pinch resistors, and diodes, all incorporating transition regions, are also disclosed.

Silicon oxide insulator (SOI) semiconductor having selectively linked body

Sub-quarter micron MOSFET's and ring oscillators with 2.5-6 nm physical gate oxide thicknesses have been studied at supply voltages of 1.5-3.3 V. I/sub dsat/ can be accurately predicted from a universal mobility model and a current model considering velocity saturation and parasitic series resistance. Gate delay and the optimal gate oxide thickness were modeled and predicted. Optimal gate oxide thicknesses for different interconnect loading are highlighted.

Donald L. Wollesen

Papers

Short channel self-aligned VMOS field effect transistor

High conductivity interconnection line

Trench-gated vertical combination JFET and MOSFET devices

Silicon oxide insulator (SOI) semiconductor having selectively linked body

Predicting CMOS speed with gate oxide and voltage scaling and interconnect loading effects