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Dong Xiang
Researcher at Tsinghua University
Publications - 129
Citations - 1316
Dong Xiang is an academic researcher from Tsinghua University. The author has contributed to research in topics: Automatic test pattern generation & Scan chain. The author has an hindex of 20, co-authored 129 publications receiving 1206 citations. Previous affiliations of Dong Xiang include University of Illinois at Urbana–Champaign & University of Nebraska–Lincoln.
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Products made from nonmetallic materials reclaimed from waste printed circuit boards
TL;DR: In this paper, a study of the reclaimation and reuse of non-metallic materials recovered from waste printed circuit boards (PCBs) was presented, and the recovered nonmetals were used to make models, construction materials, composite boards, sewer grates, and amusement park boats.
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Practical Deadlock-Free Fault-Tolerant Routing in Meshes Based on the Planar Network Fault Model
Dong Xiang,Yueli Zhang,Yi Pan +2 more
TL;DR: A new deadlock avoidance technique is proposed for 3D meshes using only two virtual channels by making full use of the idle channels in a deadlock-free adaptive fault-tolerant routing scheme based on a planar network (PN) fault model.
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Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction
TL;DR: It is shown that test application cost, test data volume, and test power with the proposed scan forest architecture can be greatly reduced compared with the conventional full scan design with a single scan chain and several recent scan testing methods.
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Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding
TL;DR: A new low-power (LP) scan-based built-in self-test (BIST) technique is proposed based on weighted pseudorandom test pattern generation and reseeding, which supports both pseud orandom testing and deterministic BIST.
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Cost-Effective Power-Aware Core Testing in NoCs Based on a New Unicast-Based Multicast Scheme
Dong Xiang,Ye Zhang +1 more
TL;DR: A new power-aware test scheduling scheme is proposed, which is extended to cases for multiple port ATEs and Experimental results are presented to show the effectiveness of the proposed method in reducing the NoC test cost and test data volume by comparing to the previous methods.