This brief presents an inductorless $g_{m}$ -boosted wideband balun low noise amplifier (LNA) for low power sub-GHz IoT applications. The proposed common source (CS) - common gate (CG) based $g_{m}$ -boosted balun LNA uses nMOS-pMOS configuration for doubling the transconductance and gain efficiency. Loads of CS and CG stages are capacitively coupled to remove the tradeoff between voltage gain and voltage headroom. In addition to this, the circuit employs noise cancelation using the CS-CG pair. The LNA is implemented in 0.18 $\mu \text{m}$ RFCMOS process, which achieves a maximum voltage gain of 19.6 dB with a minimum noise figure (NF) of 3.6 dB. The 3-dB bandwidth ranges from 0.13 GHz to 0.93 GHz. The minimum IIP3 and IIP2 measured are −8.5 dBm and 12 dBm, respectively. The LNA core area is 0.18 $mm^{2}$ and dissipates a total power of 3 mW from 1.8 V power supply.

An Inductorless Wideband Gm-Boosted Balun LNA With nMOS-pMOS Configuration and Capacitively Coupled Loads for Sub-GHz IoT Applications

In this paper, a wideband low-noise amplifier (LNA) with a two-fold noise cancellation scheme is proposed. Finetuned for advanced CMOS, the proposed LNA architecture uses a common-gate input branch to provide wideband input matching. It is followed by two stages of the common-source structure which cancels the noise and distortion of the first and second stages and relaxes the design restriction on the first noise-cancellation stage. The provided circuit-level analysis is verified by simulations. The proposed LNA is fabricated in 28-nm CMOS. It achieves a minimum noise figure (NF) of 2.5dB and input return loss (S<sub>11</sub>) &#x003C; &#x2212;15dB over 0.02&#x2013;2GHz bandwidth while consuming only 4.1mW from a 1V supply and driving an external 50-<inline-formula> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> load. The &#x2212;3dB power gain (S<sub>21</sub>) is 18.5dB and IIP3 is &#x002B;4.25dBm. 

A 20 MHz–2 GHz Inductorless Two-Fold Noise-Canceling Low-Noise Amplifier in 28-nm CMOS

A broadband process, voltage, and temperature (PVT)-insensitive noise-canceling balun-low-noise amplifier (LNA) was implemented in the 0.13- $\mu \text{m}$ CMOS process for subgigahertz wireless communication applications. The proposed LNA is based on the traditional common-gate common-source (CGCS) balun-LNA topology, and it adopts the diode-connected loads to reduce the noise contribution originated from CGCS transistors and enhance the linearity due to post linearization. The auxiliary common-source (CS) amplifier with a diode-connected is added to reduce the overall noise figure (NF) of the LNA by sharing an input signal with CGCS transistors and applying its output signal to the diode-connected load of CS transistor. Because the voltage gain of the LNA is determined by the transconductance ( $g_{m}$ ) ratio of the same types of nMOS transistors, its power gain ( $S_{21}$ ) and NF are quite roust over PVT variations. In experiments, it showed $S_{21}$ of 14 dB and NF of 4 dB with an input return loss ( $S_{11}$ ) of greater than 10 dB at 450 MHz. Concerning voltage variation (1.08–1.32 V) and temperature variation ( $- 20\,\,^{\circ }\text {C} \sim +80 \,\,^{\circ }\text{C}$ ), the worst variations in $S_{21}$ and NF were approximately 1.4 and 1.1 dB, respectively.

A Broadband PVT-Insensitive All-nMOS Noise-Canceling Balun-LNA for Subgigahertz Wireless Communication Applications

: This paper presents a low-noise ampliﬁer (LNA) with single to differential conversion (Balun) for multi-standard radio applications. The proposed LNA combines a common-gate (CG) stage for wideband input matching and a common-source (CS) stage to cancel the noise and distortion of the CG stage. Using the proposed technique, a low noise ﬁgure (NF) is achieved while providing a wideband of operation. Furthermore, a feedback connection from the CS stage to the gate of the CG is employed to boost the transconductance of the CG stage ( gm CG ), and an additional complementary transistor is applied at the CS stage using current reuse to increase the overall transconductance of the CS stage ( gm CS ) without increasing the power consumed by the stage. This LNA was designed using TSMC 65 nm technology, and post-layout simulation results show operation across 0.5–5 GHz, a maximum power gain of 20 dB, 4 dB minimum NF, and third-order intercept point (IIP3) of − 10 dBm while consuming only 5 mW of power from a 1.2 V supply.

A Wideband Low-Power Balun-LNA with Feedback and Current Reuse Technique

This paper presents a low-noise amplifier (LNA) with single to differential conversion (Balun) for multi-standard radio applications. The proposed LNA combines a common-gate (CG) stage for wideband input matching and a common-source (CS) stage to cancel the noise and distortion of the CG stage. Using the proposed technique, a low noise figure (NF) is achieved while providing a wideband of operation. Furthermore, a feedback connection from the CS stage to the gate of the CG is employed to boost the transconductance of the CG stage (gmCG), and an additional complementary transistor is applied at the CS stage using current reuse to increase the overall transconductance of the CS stage (gmCS) without increasing the power consumed by the stage. This LNA was designed using TSMC 65 nm technology, and post-layout simulation results show operation across 0.5–5 GHz, a maximum power gain of 20 dB, 4 dB minimum NF, and third-order intercept point (IIP3) of −10 dBm while consuming only 5 mW of power from a 1.2 V supply. 

/pdf/a-wideband-low-power-balun-lna-with-feedback-and-current-3siscgb1.pdf

This paper presents an ultra-low power, low cost demodulator for gaussian frequency shift keying (GFSK) receivers that use low intermediate frequencies (IF). The demodulator employs a direct IF to digital data conversion scheme by using an injection-locked ring oscillator (ILRO) with a 1-bit flip-flop. It consumes $2.7~\mu \text{W}$ from a 1.0 V supply at a data rate of 500 kbps achieving an energy efficiency of 5.4 pJ/bit which is 30 times better than that of the recently presented works. The demodulator also achieves 17.5 dB SNR at 0.1 % BER while operating at the same date rate. The demodulator is implemented in a $0.18~\mu \text{m}$ standard CMOS process and occupies an active area of 0.012 mm2.

/pdf/a-1-0-v-5-4-pj-bit-gfsk-demodulator-based-on-an-injection-1sq5fw1wz8.pdf

A 1.0 V, 5.4 pJ/bit GFSK Demodulator Based on an Injection Locked Ring Oscillator for Low-IF Receivers

A process, voltage, and temperature (PVT) insensitive noise canceling blaun-LNA is implemented in 0.13μm CMOS process for TV receiver applications. The proposed balun-LNA is composed of only NMOS transistors, and its voltage gain is determined by transconductance (g m ) ratio of the transistors of the same type. This makes the voltage gain and NF of the LNA insensitive to PVT variations. In addition, the unity gain CS amplifier with diode-connected load is added in order to reduce the noise contribution from the CS stage in the proposed balun LNA. In spite of the additional noise contribution from the unity gain CS amplifier, the proposed LNA improves the overall noise figure (NF) performance. In the post-layout simulation, the proposed balun-LNA shows a power gain (S 21 ) of 14.5 dB, a NF of less than 2.6 dB, an input return loss (S 11 ) of greater than 10dB at 500 MHz and typical corner condition (tt, 1.2 V, 27°C). The variation of S 21 and NF at 500 MHz is about 2.5dB and 0.8 dB, respectively, over all corner variations. The power consumption of the proposed balun-LNA excluding the output buffer is about 3.6mW at a 1.2V supply.

A PVT insensitive noise canceling balun-LNA for TV receiver applications

This work presents a high efficiency RF-to-DC conversion circuit composed of an LC-CL balun-based Gm-boosting envelope detector, a low noise baseband amplifier, and an offset canceled latch comparator. It was designed to have high sensitivity with low power consumption for wake-up receiver (WuRx) applications. The proposed envelope detector is based on a fully integrated inductively degenerated common-source amplifier with a series gate inductor. The LC-CL balun circuit is merged with the core of the envelope detector by sharing the on-chip gate and source inductors. The proposed technique doubles the transconductance of the input transistor of the envelope detector without any extra power consumption because the gate and source voltage on the input transistor operates in a differential mode. This results in a higher RF-to-DC conversion gain. In order to improve the sensitivity of the wake-up radio, the DC offset of the latch comparator circuit is canceled by controlling the body bias voltage of a pair of differential input transistors through a binary-weighted current source cell. In addition, the hysteresis characteristic is implemented in order to avoid unstable operation by the large noise at the compared signal. The hysteresis window is programmable by changing the channel width of the latch transistor. The low noise baseband amplifier amplifies the output signal of the envelope detector and transfers it into the comparator circuit with low noise. For the 2.4 GHz WuRx, the proposed envelope detector with no external matching components shows the simulated conversion gain of about 16.79 V/V when the input power is around the sensitivity of −60 dBm, and this is 1.7 times higher than that of the conventional envelope detector with the same current and load. The proposed RF-to-DC conversion circuit (WuRx) achieves a sensitivity of about −65.4 dBm based on 45% to 55% duty, dissipating a power of 22 μW from a 1.2 V supply voltage.

A High Efficiency Low Noise RF-to-DC Converter Employing Gm-Boosting Envelope Detector and Offset Canceled Latch Comparator

A highly linear super-source-follower (super SF) based reconfigurable RF filter with wide tuning range is proposed for TV receiver applications By converting the polarity of the differential output signals of the super SF through CMOS switches, the transfer function of the conventional Sallen-Key (SK) filter can be easily changed to have lower 3-dB cutoff frequency without increasing the total capacitance of the switched capacitor array This greatly reduces the chip size of the proposed tunable filter while maximizing the frequency tuning range The proposed tunable SK filter was implemented in 013μm CMOS technology In the post-layout simulation, the proposed SK filter 76MHz ∼ 16 GHz frequency tuning range, NF of less than 147dB The power consumption of the tunable filter excluding input/output buffer is 318 mW at a 12 V supply

Donggu Im

Papers

A Broadband PVT-Insensitive All-nMOS Noise-Canceling Balun-LNA for Subgigahertz Wireless Communication Applications

A 1.0 V, 5.4 pJ/bit GFSK Demodulator Based on an Injection Locked Ring Oscillator for Low-IF Receivers

A PVT insensitive noise canceling balun-LNA for TV receiver applications

A High Efficiency Low Noise RF-to-DC Converter Employing Gm-Boosting Envelope Detector and Offset Canceled Latch Comparator

A highly linear super-source-follower-based reconfigurable RF filter with wide tuning range for TV receiver applications