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[서평]「Computer Organization and Design, The Hardware/Software Interface」

A system, method, and computer program product are provided for a touch or pressure signal-based interface. In operation, a touch or pressure signal is received in association with a touch interface of a device. To this end, a user experience is altered utilizing the signal. A system, method, and computer program product are provided for modifying one or more objects in one or more memory devices. In one embodiment, an apparatus is provided, comprising one or more memory devices including a non-volatile memory. Additionally, the apparatus comprises circuitry including a first communication path for communicating with the at least one processor, and a second communication path for communicating with at least one storage sub-system which operates slower than the one or more memory devices. Further, the circuitry is operable to modify one or more objects in the one or more memory devices.

User interface system, method, and computer program product

Theminimum-degree greedy algorithm, or Greedy for short, is a simple and well-studied method for finding independent sets in graphs. We show that it achieves a performance ratio of (Δ+2)/3 for approximating independent sets in graphs with degree bounded by Δ. The analysis yields a precise characterization of the size of the independent sets found by the algorithm as a function of the independence number, as well as a generalization of Turan's bound. We also analyze the algorithm when run in combination with a known preprocessing technique, and obtain an improved $$(2\bar d + 3)/5$$ performance ratio on graphs with average degree $$\bar d$$ , improving on the previous best $$(\bar d + 1)/2$$ of Hochbaum. Finally, we present an efficient parallel and distributed algorithm attaining the performance guarantees of Greedy.

Greed is good : approximating independent sets in sparse and bounded-degree graphs

Designing multi-processor systems-on-chips becomes increasingly complex, as more applications with realtime requirements execute in parallel. System resources, such as memories, are shared between applications to reduce cost, causing their timing behavior to become inter-dependent. Using conventional simulation-based verification, this requires all concurrently executing applications to be verified together, resulting in a rapidly increasing verification complexity. Predictable and composable systems have been proposed to address this problem. Predictable systems provide bounds on performance, enabling formal analysis to be used as an alternative to simulation. Composable systems isolate applications, enabling them to be verified independently. Predictable and composable systems are built from predictable and composable resources. This paper presents three general techniques to implement and model predictable and composable resources, and demonstrates their applicability in the context of a memory controller. The architecture of the memory controller is general and supports both SRAM and DDR2/DDR3 SDRAM and a wide range of arbiters, making it suitable for many predictable and composable systems. The modeling approach is based on a shared-resource abstraction that covers any combination of supported memory and arbiter and enables system-level performance analysis with a variety of well-known frameworks, such as network calculus or data-flow analysis.

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Architectures and modeling of predictable memory controllers for improved system integration

Part 1: Application Mapping and Communication Infrastructure: Virtualization in NOCs--Enhanced MPSOC Robustness and Performance Verification.-HW Support to Exploit Parallelism in Homogeneous and Heterogeneous Multicore System-on-Chip.-PALLAS: Mapping Applications onto Manycore.-Part 2: Reconfigurable Hardware in Multiprocessor Systems: Adaptive Multiprocessor System on Chip Architecture.-Designing FPGA Systems with Many Processors.-Part 3: Physical Design of Multiprocessor Systems: Design tools and methods for chip physical design.-Challenges in Physical Design for Multi- and Manycore Hardware Architectures.

Multiprocessor System-on-Chip

Transport Triggered Architectures (TTAs) possess many advantageous, such as modularity, flexibility, and scalability. As an exposed datapath architecture, TTAs can effectively reduce the register file (RF) pressure in both number of accesses and number of RF ports. However, the conventional TTAs also have some evident disadvantages, such as relative low code density, dynamic-power wasting due to separate scheduling of source operands, and inefficient support for variant immediate values. In order to preserve the merit of conventional TTAs, while solving these aforementioned issues, we propose, MOVE-Pro, a novel low power and high code density TTA architecture. With optimizations at instruction set architecture (ISA), architecture, circuit, and compiler levels, the low-power potential of TTAs is fully exploited. Moreover, with a much denser code size, TTAs performance is also improved accordingly. In a head-to-head comparison between a two-issue MOVE-Pro processor and its RISC counterpart, we shown that up to 80% of RF accesses can be reduced, and the reduction in RF power is successfully transferred to the total core power saving. Up to 11% reduction of the total core power is achieved by our MOVE-Pro processor, while the code density is almost the same as its RISC counterpart.

MOVE-Pro: A low power and high code density TTA architecture

Processor virtualization divides a physical processor's time among a set of virual machines, enabling efficient hardware utilization, application security and allowing co-existence of different operating systems on the same processor. Through initially intended for the server domain, virtualization gains popularity also in embemmed systems, where it is mainly meant to isolate real-time from best effort applications, as they require different types of schedulers and performance guarantees. More-over, for design productivity and cost reasons, one would like to indepently design, test, and verify applications, then easily integrate them on a shared hardware platform. For best effort, this requires composable capacity, i.e. an application's number of processor cycles is independent of other applications. In real-time, performance prediction and guarantees preservation is crucial, thus the timing of an application's cycles should also be indepent, i.e. composable performance/timing. Virtualization is a good first step towards these, however existing approaches do not ensure timing composability. In this paper we propose a processor virtualization scheme with: (1) composable timing and capacity, and (2) different task schedulers per application. This scheme is based on: (1) a budget-based scheduler for composable capacity, plus (2) the ability to program application switching at fixed points in time, for composable timing. We implemented this scheme on an FPGA multiprocessor running a synthetic application and experiments show composability.

Composable processor virtualization for embedded systems

Composability means that the behaviour of an application, including its timing, is not affected by the absence or presence of other applications. It is required to be able to design, test, and verify applications independently. In this paper we define composable dynamic voltage and frequency scaling (DVFS) hardware, and composable power management. We ensure that the functional and temporal behaviours of an application are not affected by other applications, even when they are power managed. For dataflow applications with worst-case execution times per task, our power management is also predictable, i.e. guarantees end-to-end real-time requirements, even when the application is mapped on multiple processors that are power managed independently. Our method can be used with various DVFS architectures, such as on-chip and off-chip VF regulators. Our FPGA implementation models a system with multiple tiles, each containing a processor with local memory running a real-time operating system (RTOS) and power management. Tiles are interconnected by a network on chip, and communicate using shared memories. Experiments indicate energy savings of 68% w.r.t. no power management, and 40% w.r.t. power gating only. We also demonstrate composability and predictability on the platform in the presence of power management.

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Composable Dynamic Voltage and Frequency Scaling and Power Management for Dataflow Applications

In modern processor architectures, the register file (RF) consumes considerable amount of the processor power. It is well known that by allowing software to have explicit fine-grained control over the datapath, the transport-triggered architectures (TTAs) can substantially reduce the RF traffic, thereby minimizing the RF energy. However, it is important to make sure that the gain in RF is not cancelled out by the overhead due to the fine-grained datapath control, in particular, the deterioration of code density in conventional TTAs. In this paper, we analyze the potential of minimizing RF energy in MOVE-Pro, a TTA-based processor framework. We present a flexible compiler backend, which performs energy-aware instruction scheduling to push the limit of RF energy reduction. The experimental results show that with the proposed energy-aware compiler backend, MOVE-Pro is able to significantly reduce RF energy compared to its RISC/VLIW counterparts, by up to 80%. Meanwhile the code density of MOVE-Pro remains at the same level as its RISC/VLIW counterparts, allowing the energy saving in RF to be successfully transferred to total energy saving.

Scheduling for register file energy minimization in explicit datapath architectures

Visual servoing has been proven to obtain better performance than mechanical encoders for position acquisition. However, the often computationally intensive vision algorithms and the ever growing demands for higher frame rate make its realization very challenging. This work performs a case study on a typical industrial application, organic light emitting diode (OLED) screen printing, and demonstrates the feasibility of achieving ultra high frame rate visual servoing applications on both field programmable gate array (FPGA) and single instruction multiple data (SIMD) processors. We optimize the existing vision processing algorithm and propose a scalable FPGA implementation, which processes a frame within 102 µs. Though a dedicated FPGA implementation is extremely efficient, lack of flexibility and considerable amount of implementation time are two of its clear drawbacks. As an alternative, we propose a reconfigurable wide SIMD processor, which balances among efficiency, flexibility, and implementation effort. For input frames of 120 × 45 resolution, our SIMD can process a frame within 232 µs, sufficient to provide a throughput of 1000fps with less than 1ms latency for the whole vision servoing system. Compared to the reference realization on MicroBlaze, the proposed SIMD processor achieves a 21× performance improvement.

Dongrui She

Papers

MOVE-Pro: A low power and high code density TTA architecture

Composable processor virtualization for embedded systems

Composable Dynamic Voltage and Frequency Scaling and Power Management for Dataflow Applications

Scheduling for register file energy minimization in explicit datapath architectures

Feasibility analysis of ultra high frame rate visual servoing on FPGA and SIMD processor