The controlled synthesis of materials by methods that permit their assembly into functional nanoscale structures lies at the crux of the emerging field of nanotechnology. Although only one of several materials families is of interest, carbon-based nanostructured materials continue to attract a disproportionate share of research effort, in part because of their wide-ranging properties. Additionally, developments of the past decade in the controlled synthesis of carbon nanotubes and nanofibers have opened additional possibilities for their use as functional elements in numerous applications. Vertically aligned carbon nanofibers (VACNFs) are a subclass of carbon nanostructured materials that can be produced with a high degree of control using catalytic plasma-enhanced chemical-vapor deposition (C-PECVD). Using C-PECVD the location, diameter, length, shape, chemical composition, and orientation can be controlled during VACNF synthesis. Here we review the CVD and PECVD systems, growth control mechanisms, catalyst preparation, resultant carbon nanostructures, and VACNF properties. This is followed by a review of many of the application areas for carbon nanotubes and nanofibers including electron field-emission sources, electrochemical probes, functionalized sensor elements, scanning probe microscopy tips, nanoelectromechanical systems (NEMS), hydrogen and charge storage, and catalyst support. We end by noting gaps in the understanding of VACNF growth mechanisms and the challenges remaining in the development of methods for an even more comprehensive control of the carbon nanofiber synthesis process.

Vertically Aligned Carbon Nanofibers and Related Structures: Controlled Synthesis and Directed Assembly

A chalcogenide memory cell with chalcogenide electrodes positioned on both sides of the active chalcogenide region of the memory cell. The chalcogenide memory cell includes upper and lower chalcogenide electrodes with a dielectric layer positioned therebetween. The dielectric layer includes an opening defining a pore. A volume of chalcogenide material formed integral to the upper chalcogenide electrode is contained within the pore. The upper and lower chalcogenide electrodes both have greater cross sectional areas than the pore.

Chalcogenide memory cell with a plurality of chalcogenide electrodes

There is described a memory cell having a vertically oriented polysilicon pillar diode for use in delivering large current flow through a variable resistance material memory element. The pillar diode comprises a plurality of polysilicon layers disposed in a vertical stack between a wordline and digitline. The memory element is disposed in series with the diode, also between the wordline and the digitline. The diode is capable of delivering the large current flow required to program the memory element without also requiring the surface space on the upper surface of the memory matrix normally associated with such powerful diodes. The invention allows memory cells to be disposed every 0.7 microns or less across the face of a memory matrix. Further, the memory cell is easily fabricated using standard processing techniques. The unique layout of the inventive memory cell allows fabrication with as few as three mask steps or less.

Polysilicon pillar diode for use in a non-volatile memory cell

Silicides and ohmic contacts

A method and an apparatus for manufacturing a memory cell having a non-volatile resistive memory element with a limited size active area. The method comprises a first step of providing a dielectric volume and forming a plug opening within the dielectric volume. A recessed plug of a conductive material is then formed within a lower portion of the opening and a dielectric spacer is formed along the sidewalls of an upper portion of the opening. The spacer is cylindrical and has a central hole. A contact plug is subsequently formed within the central hole, the contact plug electrically coupled to the recessed plug. The contact plug can include a memory element or an additional memory element can be applied over the contact plug.

Method and apparatus for forming an integrated circuit electrode having a reduced contact area

A contact stud for semiconductor structure is fabricated by providing a semiconductor substrate having an alignment structure, which includes a sidewall, and the semiconductor structure formed thereon, forming a sidewall spacer contiguous with the semiconductor structure and the sidewall of the alignment structure, depositing an insulating layer contiguous with the sidewall spacer so as to insulate the semiconductor structure, etching the sidewall spacer selectively to the sidewall of the alignment structure, the semiconductor structure and the insulating layer forming a contact window opening for allowing access to the semiconductor structure, and backfilling the contact window opening with a conductive material so as to contact the semiconductor structure for forming the stud.

Process for fabricating self-aligned contact studs for semiconductor structures

A method of fabricating micro-electromechanical switches (MEMS) integrated with conventional semiconductor interconnect levels, using compatible processes and materials is described. The method is based upon fabricating a capacitive switch that is easily modified to produce various configurations for contact switching and any number of metal-dielectric-metal switches. The process starts with a copper damascene interconnect layer, made of metal conductors inlaid in a dielectric. All or portions of the copper interconnects are recessed to a degree sufficient to provide a capacitive air gap when the switch is in the closed state, as well as provide space for a protective layer of, e.g., Ta/TaN. The metal structures defined within the area specified for the switch act as actuator electrodes to pull down the movable beam and provide one or more paths for the switched signal to traverse. The advantage of an air gap is that air is not subject to charge storage or trapping that can cause reliability and voltage drift problems. Instead of recessing the electrodes to provide a gap, one may just add dielectric on or around the electrode. The next layer is another dielectric layer which is deposited to the desired thickness of the gap formed between the lower electrodes and the moveable beam that forms the switching device. Vias are fabricated through this dielectric to provide connections between the metal interconnect layer and the next metal layer which will also contain the switchable beam. The via layer is then patterned and etched to provide a cavity area which contains the lower activation electrodes as well as the signal paths. The cavity is then back-filled with a sacrificial release material. This release material is then planarized with the top of the dielectric, thereby providing a planar surface upon which the beam layer is constructed.

Method of fabricating micro-electromechanical switches on cmos compatible substrates

Plasma-assisted deposition of thin films is widely used in microelectronic circuit manufacturing. Materials deposited include conductors such as tungsten, copper, aluminum, transition-metal silicides, and refractory metals, semiconductors such as gallium arsenide, epitaxial and polycrystalline silicon, and dielectrics such as silicon oxide, silicon nitride, and silicon oxynitride. This paper reviews plasma-assisted chemical vapor deposition (CVD) applications and techniques for dielectric thin films. In particular, we focus on the integration, process, and reliability requirements for dielectric films used for isolation, passivation, barrier, and antireflectivecoating applications in ultralargescale integrated (ULSI) semiconductor circuits. In addition, manufacturing issues and considerations for further work are discussed.

Plasma-assisted chemical vapor deposition of dielectric thin films for ULSI semiconductor circuits

A process for fabricating a device including the step of forming a structure for facilitating the passivation of surface states is disclosed. The structure comprises an oxynitride layer formed as part of the device structure. The oxynitride facilitates the passivation of surface states when heated.

Semiconductor device structure with hydrogen-rich layer for facilitating passivation of surface states

Significant progress has been made over the past decade in low-temperature plasma-enhanced and thermal chemical vapor deposition (CVD). The progress has occurred in response to the high demands placed on the insulators of multilevel microelectronic circuits because of the continuing reduction in circuit dimensions. High-aspect-ratio gap filling is foremost among these demands, which also include lower processing temperatures and improved dielectric planarization. This paper reviews the history of interlevel and intermetal dielectrics used in microelectronic circuit manufacturing at IBM and the current status of processes used in IBM manufacturing and development lines, and describes the challenges for future memory and logic chip applications.

Donna R. Cote

Papers

Process for fabricating self-aligned contact studs for semiconductor structures

Method of fabricating micro-electromechanical switches on cmos compatible substrates

Plasma-assisted chemical vapor deposition of dielectric thin films for ULSI semiconductor circuits

Semiconductor device structure with hydrogen-rich layer for facilitating passivation of surface states

Low-temperature chemical vapor deposition processes and dielectrics for microelectronic circuit manufacturing at IBM