An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

The controlled synthesis of materials by methods that permit their assembly into functional nanoscale structures lies at the crux of the emerging field of nanotechnology. Although only one of several materials families is of interest, carbon-based nanostructured materials continue to attract a disproportionate share of research effort, in part because of their wide-ranging properties. Additionally, developments of the past decade in the controlled synthesis of carbon nanotubes and nanofibers have opened additional possibilities for their use as functional elements in numerous applications. Vertically aligned carbon nanofibers (VACNFs) are a subclass of carbon nanostructured materials that can be produced with a high degree of control using catalytic plasma-enhanced chemical-vapor deposition (C-PECVD). Using C-PECVD the location, diameter, length, shape, chemical composition, and orientation can be controlled during VACNF synthesis. Here we review the CVD and PECVD systems, growth control mechanisms, catalyst preparation, resultant carbon nanostructures, and VACNF properties. This is followed by a review of many of the application areas for carbon nanotubes and nanofibers including electron field-emission sources, electrochemical probes, functionalized sensor elements, scanning probe microscopy tips, nanoelectromechanical systems (NEMS), hydrogen and charge storage, and catalyst support. We end by noting gaps in the understanding of VACNF growth mechanisms and the challenges remaining in the development of methods for an even more comprehensive control of the carbon nanofiber synthesis process.

Vertically Aligned Carbon Nanofibers and Related Structures: Controlled Synthesis and Directed Assembly

A device and method for ablating tissue is disclosed comprising the steps of acquiring an anatomical image of a patient, correlating the image to the patient, guiding an ablating member within the patient while tracking the position of the ablating member in the patient, positioning the ablating member in a desired position to ablate tissue, emitting ablating energy from the ablating member to form an ablated tissue area and removing the ablating member from the patient.

Methods of using high intensity focused ultrasound to form an ablated tissue area containing a plurality of lesions

A method of forming an integrated circuit using an amorphous carbon film. The amorphous carbon film is formed by thermally decomposing a gas mixture comprising a hydrocarbon compound and an inert gas. The amorphous carbon film is compatible with integrated circuit fabrication processes. In one integrated circuit fabrication process, the amorphous carbon film is used as a hardmask. In another integrated circuit fabrication process, the amorphous carbon film is an anti-reflective coating (ARC) for deep ultraviolet (DUV) lithography. In yet another integrated circuit fabrication process, a multi-layer amorphous carbon anti-reflective coating is used for DUV lithography.

Method of depositing an amorphous carbon layer

A method of fabricating a semiconductor device includes following steps. A substrate is provided, wherein a first dielectric layer having a trench therein is formed on the substrate, a source/drain region is formed in the substrate at two sides of the trench, and a second dielectric layer is formed on the substrate in the trench. A first physical vapor deposition process is performed to form a Ti-containing metal layer in the trench. A second physical vapor deposition process is performed to form an Al layer on the Ti-containing metal layer in the trench. A thermal process is performed to anneal the Ti-containing metal layer and the Al layer so as to form a work function metal layer. A metal layer is formed to fill the trench.

Semiconductor device and method of fabricating the same

The idea of the invention is to coat the free surface of patterned Cu conducting lines in on-chip interconnections (BEOL) wiring by a 1-20 nm thick metal layer prior to deposition of the interlevel dielectric. This coating is sufficiently thin so as to obviate the need for additional planarization by polishing, while providing protection against oxidation and surface, or interface, diffusion of Cu which has been identified by the inventors as the leading contributor to metal line failure by electromigration and thermal stress voiding. Also, the metal layer increases the adhesion strength between the Cu and dielectric so as to further increase lifetime and facilitate process yield. The free surface is a direct result of the CMP (chemical mechanical polishing) in a damascene process or in a dry etching process by which Cu wiring is patterned. It is proposed that the metal capping layer be deposited by a selective process onto the Cu to minimize further processing. We have used electroless metal coatings, such as CoWP, CoSnP and Pd, to illustrate significant reliability benefits, although chemical vapor deposition (CVD) of metals or metal forming compounds can be employed.

Reduced electromigration and stressed induced migration of Cu wires by surface coating

Plasma-assisted deposition of thin films is widely used in microelectronic circuit manufacturing. Materials deposited include conductors such as tungsten, copper, aluminum, transition-metal silicides, and refractory metals, semiconductors such as gallium arsenide, epitaxial and polycrystalline silicon, and dielectrics such as silicon oxide, silicon nitride, and silicon oxynitride. This paper reviews plasma-assisted chemical vapor deposition (CVD) applications and techniques for dielectric thin films. In particular, we focus on the integration, process, and reliability requirements for dielectric films used for isolation, passivation, barrier, and antireflectivecoating applications in ultralargescale integrated (ULSI) semiconductor circuits. In addition, manufacturing issues and considerations for further work are discussed.

Plasma-assisted chemical vapor deposition of dielectric thin films for ULSI semiconductor circuits

A double-sided integrated circuit chips, methods of fabricating the double-sided integrated circuit chips and design structures for double-sided integrated circuit chips. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided.

Double-sided integrated circuit chips

An image sensor array and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack with improved thickness uniformity to result in a pixel array exhibiting increased light sensitivity. In the sensor array, each Cu metallization level includes a Cu metal wire structure formed at locations between each array pixel and, a barrier material layer is formed on top each Cu metal wire structure that traverses the pixel optical path. By implementing a single mask or self-aligned mask methodology, a single etch is conducted to completely remove the interlevel dielectric and barrier layers that traverse the optical path. The etched opening is then refilled with dielectric material. Prior to depositing the refill dielectric, a layer of either reflective or absorptive material is formed along the sidewalls of the etched opening to improve sensitivity of the pixels by either reflecting light to the underlying photodiode or by eliminating light reflections.

Anthony K. Stamper

Papers

Reduced electromigration and stressed induced migration of Cu wires by surface coating

Plasma-assisted chemical vapor deposition of dielectric thin films for ULSI semiconductor circuits

Double-sided integrated circuit chips

A damascene copper wiring image sensor

Reduced Cu interface diffusion by CoWP surface coating