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Durbadal Mandal

Researcher at National Institute of Technology, Durgapur

Publications -  454
Citations -  4262

Durbadal Mandal is an academic researcher from National Institute of Technology, Durgapur. The author has contributed to research in topics: Particle swarm optimization & Antenna array. The author has an hindex of 27, co-authored 409 publications receiving 3297 citations. Previous affiliations of Durbadal Mandal include Hindustan College of Science and Technology.

Papers
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Proceedings ArticleDOI

Optimization of Low Noise Amplifier using Particle Swarm Optimization

TL;DR: This paper presents an optimal design of a CMOS Low Noise Amplifier implemented in the inductive source degeneration topology using Particle Swarm Optimization (PSO) technique that has a substantially low noise figure with better forward gain.
Book ChapterDOI

Design of Low-Voltage CMOS Op-Amp Using Evolutionary Optimization Techniques

TL;DR: Simplex-PSO shows the better optimizing efficiency than PSO for the designed circuit and SPICE-based results demonstrate that the design and essential specifications are approximately reached.
Proceedings ArticleDOI

Application of improved Particle Swarm Optimization technique for thinning of concentric hexagonal array antenna

TL;DR: The simulation results show that the number of antenna array elements can be brought down more than 50% of total isotropic elements with simultaneous reduction in Side Lobe Level (SLL) with an approximately fixed first null beam width (FNBW).
Journal ArticleDOI

Optimal design of zero-phase digital Riesz FIR fractional-order differentiator

TL;DR: An optimal design of finite impulse response-type Riesz fractional-order digital differentiator (FODD) of orders p = 0.3, 0.5, and 0.75 is introduced and is utilized in the ECG QRS complex identification system to demonstrate its real-time application.
Proceedings ArticleDOI

Low power VLSI circuit implementation using mixed static CMOS and domino logic with delay elements

TL;DR: The problem is addressed with the realization of the circuit which requires the implementation of inverted logic using mixed static and domino logic, and the efficiency of the proposed model is considered.