The CMOS technology area has quickly grown, calling for a new text--and here it is, covering the analysis and design of CMOS integrated circuits that practicing engineers need to master to succeed. Filled with many examples and chapter-ending problems, the book not only describes the thought process behind each circuit topology, but also considers the rationale behind each modification. The analysis and design techniques focus on CMOS circuits but also apply to other IC technologies.
Table of contents

1 Introduction to Analog Design
2 Basic MOS Device Physics
3 Single-Stage Amplifiers
4 Differential Amplifiers
5 Passive and Active Current Mirrors
6 Frequency Response of Amplifiers
7 Noise
8 Feedback
9 Operational Amplifiers
10 Stability and Frequency Compensation
11 Bandgap References
12 Introduction to Switched-Capacitor Circuits
13 Nonlinearity and Mismatch
14 Oscillators
15 Phase-Locked Loops
16 Short-Channel Effects and Device Models
17 CMOS Processing Technology
18 Layout and Packaging

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Design of Analog CMOS Integrated Circuits

Radio frequency integrated circuits (RFICs) are the building blocks that enable every device from cable television sets to mobile telephones to transmit and receive signals and data. This newly revised and expanded edition of the 2003 Artech House classic, "Radio Frequency Integrated Circuit Design", serves as an up-to-date, practical reference for complete RFIC know-how. The second edition includes numerous updates, including greater coverage of CMOS PA design, RFIC design with on-chip components, and more worked examples with simulation results. By emphasizing working designs, this book practically transports readers into the authors' own RFIC lab so they can fully understand how these designs function. This title is suitable for radio frequency integrated circuit (RFIC) design engineers; radio systems architects; researchers and developers of RFIC technology; and, graduate level electrical engineering students.

Radio Frequency Integrated Circuit Design

A consistent one-dimensional distributed electromechanical model of an electrically actuated narrow microbeam with width/height between 0.5–2.0 is derived, and the needed pull-in parameters are extracted with different methods. The model accounts for the position-dependent electrostatic loading, the fringing field effects due to both the finite width and the finite thickness of a microbeam, the mid-plane stretching, the mechanical distributed stiffness, and the residual axial load. Both clamped–clamped and clamped-free (cantilever) microbeams are considered. The method of moments is used to estimate the electrostatic load. The resulting nonlinear fourth-order differential equation under appropriate boundary conditions is solved by two methods. Initially, a one-degree-of-freedom model is proposed to find an approximate solution of the problem. Subsequently, the meshless local Petrov–Galerkin (MLPG) and the finite-element (FE) methods are used, and results from the three methods are compared. For the MLPG method, the kinematic boundary conditions are enforced by introducing a set of Lagrange multipliers, and the trial and the test functions are constructed using the generalized moving least-squares approximation. The nonlinear system of algebraic equations arising from the MLPG and the FE methods are solved by using the displacement iteration pull-in extraction (DIPIE) algorithm. Three-dimensional FE simulations of narrow cantilever and clamped–clamped microbeams are also performed with the commercial code ANSYS. Furthermore, computed results are compared with those arising from other distributed models available in the literature, and it is shown that improper fringing fields give inaccurate estimations of the pull-in voltages and of the pull-in deflections. 1641

Electromechanical Model of Electrically Actuated Narrow Microbeams

A simple computationally efficient closed-form model has been developed to determine the pull-in voltage of a cantilever beam actuated by electrostatic force. The approach is based on a linearized uniform approximate model of the nonlinear electrostatic pressure and the load deflection model of a cantilever beam under uniform pressure. The linearized electrostatic pressure includes the electrostatic pressure due to the fringing field capacitances and has been derived from Meijs and Fokkema's highly accurate empirical expression for the capacitance of a VLSI on-chip interconnect. The model has been verified by comparing the results with published experimentally verified 3D finite element analysis results and also with results from similar closed-form models. The new model can evaluate the pull-in voltage for a cantilever beam with a maximum deviation of ±2% from the finite element analysis results for wide beams, and a maximum deviation of ±1% for narrow beams (extreme fringing field).

https://iopscience.iop.org/article/10.1088/0960-1317/15/4/012/pdf

A closed-form model for the pull-in voltage of electrostatically actuated cantilever beams

The work presents new formulas for the capacitances of the most common two-dimensional (2-D) interconnect structures. The results have been obtained by using a physically-based approach: each geometry has been divided into elementary components studied rigorously with the conformal mapping method. The capacitances of structures composed by one, two, or three lines on a ground plane are then written as a weighted sum of such elements. Since the elementary terms already account for the correct geometrical dependencies, very few numerical simulations have been required to tailor the formulas, attaining an accuracy higher than previously known results, over a wide range of the geometrical parameters of the lines.

New formulas of interconnect capacitances based on results of conformal mapping method

A comparison is made between various approximations of the line-to-ground capacitance problem in a VLSI environment. It is shown that with up-to-date dimensions, the simple parallel-plate model is no longer adequate. However, easy-to-use and fast-to-compute formulas exist that result in accurate and reliable capacitance values. >

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E. Barke

Papers

Line-to-ground capacitance calculation for VLSI: a comparison