With a global market share of about 90%, crystalline silicon is by far the most important photovoltaic technology today. This article reviews the dynamic field of crystalline silicon photovoltaics from a device-engineering perspective. First, it discusses key factors responsible for the success of the classic dopant-diffused silicon homojunction solar cell. Next it analyzes two archetypal high-efficiency device architectures – the interdigitated back-contact silicon cell and the silicon heterojunction cell – both of which have demonstrated power conversion efficiencies greater than 25%. Last, it gives an up-to-date summary of promising recent pathways for further efficiency improvements and cost reduction employing novel carrier-selective passivating contact schemes, as well as tandem multi-junction architectures, in particular those that combine silicon absorbers with organic–inorganic perovskite materials.

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High-efficiency crystalline silicon solar cells: status and perspectives

Ever since the first publications by R.J. Schwartz in 1975, research into back-contact cells as an alternative to cells with a front and rear contact has remained a research topic. In the last decade, interest in back-contact cells has been growing and a gradual introduction to industrial applications is emerging. The goal of this review is to present a comprehensive summary of results obtained throughout the years. Back-contact cells are divided into three main classes: back-junction (BJ), emitter wrap-through (EWT) and metallisation wrap-through (MWT), each introduced as logical descendents from conventional solar cells. This deviation from the chronology of the developments is maintained during the discussion of technological results. In addition to progress on manufacturing these cells, aspects of cell modelling and module manufacturing are discussed and an outlook towards industrial implementation is presented. Copyright © 2005 John Wiley & Sons, Ltd.

Back-contact solar cells : A review

In May 2010 the United States National Science Foundation sponsored a two-day workshop to review the state-of-the-art and research challenges in photovoltaic (PV) manufacturing. This article summarizes the major conclusions and outcomes from this workshop, which was focused on identifying the science that needs to be done to help accelerate PV manufacturing. A significant portion of the article focuses on assessing the current status of and future opportunities in the major PV manufacturing technologies. These are solar cells based on crystalline silicon (c-Si), thin films of cadmium telluride (CdTe), thin films of copper indium gallium diselenide, and thin films of hydrogenated amorphous and nanocrystalline silicon. Current trends indicate that the cost per watt of c-Si and CdTe solar cells are being reduced to levels beyond the constraints commonly associated with these technologies. With a focus on TW/yr production capacity, the issue of material availability is discussed along with the emerging technologies of dye-sensitized solar cells and organic photovoltaics that are potentially less constrained by elemental abundance. Lastly, recommendations are made for research investment, with an emphasis on those areas that are expected to have cross-cutting impact.

Photovoltaic manufacturing: Present status, future prospects, and research needs

Flexible and stretchable electronics can dramatically enhance the application of electronics for the emerging Internet of Everything applications where people, processes, data and devices will be integrated and connected, to augment quality of life. Using naturally flexible and stretchable polymeric substrates in combination with emerging organic and molecular materials, nanowires, nanoribbons, nanotubes, and 2D atomic crystal structured materials, significant progress has been made in the general area of such electronics. However, high volume manufacturing, reliability and performance per cost remain elusive goals for wide commercialization of these electronics. On the other hand, highly sophisticated but extremely reliable, batch-fabrication-capable and mature complementary metal oxide semiconductor (CMOS)-based technology has facilitated tremendous growth of today's digital world using thin-film-based electronics; in particular, bulk monocrystalline silicon (100) which is used in most of the electronics existing today. However, one fundamental challenge is that state-of-the-art CMOS electronics are physically rigid and brittle. Therefore, in this work, how CMOS-technology-enabled flexible and stretchable electronics can be developed is discussed, with particular focus on bulk monocrystalline silicon (100). A comprehensive information base to realistically devise an integration strategy by rational design of materials, devices and processes for Internet of Everything electronics is offered.

CMOS-Technology-Enabled Flexible and Stretchable Electronics for Internet of Everything Applications.

Kerf-less removal of surface layers of photovoltaic materials including silicon, germanium, and III-Vs is demonstrated by controlled spalling technology. The method is extremely simple, versatile, and applicable to a wide range of substrates. Controlled spalling technology requires a stressor layer, such as Ni, to be deposited on the surface of a brittle material, and the controlled removal of a continuous surface layer could be performed at a predetermined depth by manipulating the thickness and stress of the Ni layer. Because the entire process is at room temperature, this technique can be applied to kerf-free ingot dicing, removal of preformed p-n junctions or epitaxial layers, or even completed devices. We successfully demonstrate kerf-free ingot dicing, as well as the removal of III-V single-junction epitaxial layers from a Ge substrate. Solar cells formed on the spalled and transferred single-junction layers showed similar characteristics to nonspalled (bulk) cells, indicating that the quality of the epitaxial layers is not compromised as a result of spalling.

Kerf-Less Removal of Si, Ge, and III–V Layers by Controlled Spalling to Enable Low-Cost PV Technologies

A new implantation-free lift-off process is presented. We deposit a layer with mismatched thermal expansion coefficient with respect to the substrate. Upon cooling, the differential contraction induces a large stress field which is released by the initiation and the propagation of a crack parallel to the surface. The principle is demonstrated on both single and multi-crystalline silicon. Films with an area of 25 cm2 and a thickness of 30–50 μm have been obtained. Some Si layers were further processed into solar cells. An energy conversion efficiency of 9.9% was reached on a 1 cm2 sample.

Stress-induced large-area lift-off of crystalline Si films

High-efficiency low-cost integral screen-printing multicrystalline silicon solar cells

This paper describes an integrated approach towards the realisation of modules based on rear contacted solar cells joining experiences in cell and module manufacturing. While research is ongoing on novel interconnection schemes, from an analysis of different possibilities, a methodology was selected that allows the introduction of the interconnection approach within a production line with minor investments. To support the suggested methodology a number of structural changes were required in the Metallisation Wrap Through cells. However, as these were limited to the layout of the contact pattern, no changes to the established cell process were needed except for the introduction of new screens. Based on the developed simple planar interconnection technology, a number of modules was manufactured with large area (100cm/sup 2/) multi-crystalline rear contacted solar cells demonstrating the electrical added value of rear contacted solar cells and attaining power densities of over 145 W/m/sup 2/.

Record high performance modules based on screen printed MWT solar cells

In this work, the authors present a circuit model to perform multidimensional solar cell simulations. This model allows for incorporating effects of lateral current flows in solar cells, keeping the required time and computer resources relatively low. The use and sensitivity of the model are described based on its application towards the design of metallisation patterns for locally passivated back surface structures. As a second application, they present the usage of the model to study the influence of different cell parameters such as surface recombination velocities and cell thickness on its performance.

E. Van Kerschaver

Papers

Stress-induced large-area lift-off of crystalline Si films

High-efficiency low-cost integral screen-printing multicrystalline silicon solar cells

Record high performance modules based on screen printed MWT solar cells

Twodimensional solar cell simulations by means of circuit modelling

Comparison of n- and p-Type High Efficiency Silicon Solar Cell Performance Under Low Illumination Conditions