I-CYP binding sites) was determinedafter 24 hours of isoproterenol treatment and ex-pressed as the percentage of receptor number as-sessed in nonstimulated cells. Where necessary,MG132 (20 mM) or lactacystin (20 mM) mixed inserum-free media was added to cells 1 hour beforestimulation.16. P. van Kerkhof, R. Govers, C. M. Alves dos Santos, G. J.Strous,

https://cml.harvard.edu/assets/science294_1313.pdf

Logic Gates and Computation from Assembled Nanowire Building Blocks

In the future, we expect commodity hardware to be used in safety-critical applications. However, in the future commodity hardware is expected to become less reliable and more susceptible to soft errors because of decreasing feature size and reduced power supply. Thus, software-implemented approaches to deal with unreliable hardware will be needed. To simplify the handling of value failures, we provide failure virtualization in the sense that we transform arbitrary value failures caused by erroneous execution into fail-stop failures. The latter ones are easier to handle. Therefore, we use the arithmetic AN-code because it provides very good error detection capabilities. Arithmetic codes are suitable for the protection of commodity hardware because guarantees can be provided independent of the executing hardware. This paper presents the encoding compiler EC-AN which applies AN-encoding to arbitrary programs. According to our knowledge, this is the first in software implemented complete AN-encoding. Former encoding compilers either encode only small parts of applications or trade-off safety to enable complete AN-encoding.

/pdf/an-encoding-compiler-building-safety-critical-systems-with-1c1gif9sfo.pdf

AN-Encoding Compiler: Building Safety-Critical Systems with Commodity Hardware

This paper presents a hybrid technique based on software signatures and a hardware module with watchdog and decoder characteristics to detect SEU and SET faults in microprocessors. These types of faults have a major influence in the microprocessor's control-flow, affecting the basic blocks and the transitions between them. In order to protect the transitions between basic blocks a light hardware module is implemented in order to spoof the data exchanged between the microprocessor and its memory. Since the hardware alone is not capable of detecting errors inside the basic blocks, it is enhanced to support the new technique and then provide full control-flow protection. A fault injection campaign is performed using a MIPS microprocessor. Simulation results show high detection rates with a small amount of performance degradation and area overhead.

Detecting SEEs in Microprocessors Through a Non-Intrusive Hybrid Technique

This paper presents HETA, a hybrid technique based on assertions and a non-intrusive enhanced watchdog module to detect SEE faults in microprocessors. These types of faults have a major influence in the microprocessor's control flow, causing incorrect jumps in the program's execution flow. In order to protect the system, a non-intrusive hardware module is implemented in order to monitor the data exchanged between the microprocessor and its memory. Since the hardware itself is not capable of detecting all control flow errors, it is enhanced to support a new software-based technique. Also, previous techniques are used to reach higher detection rates. A fault injection campaign is performed using a MIPS microprocessor. Simulation results show high detection rates with a small amount of performance degradation and area overhead.

HETA: Hybrid Error-Detection Technique Using Assertions

Due to the continuously decreasing feature sizes and the increasing complexity of integrated circuits, commercial off-the-shelf (COTS) hardware is becoming less and less reliable. However, dedicated reliable hardware is expensive and usually slower than commodity hardware. Thus, economic pressure will most likely result in the usage of unreliable COTS hardware in safety-critical systems. The usage of unreliable, COTS hardware in safety-critical systems results in the need for software-implemented solutions for handling execution errors caused by this unreliable hardware. In this thesis, we provide techniques for detecting hardware errors that disturb the execution of a program. The detection provided facilitates handling of these errors, for example, by retry or graceful degradation. We realize the error detection by transforming unsafe programs that are not guaranteed to detect execution errors into safe programs that detect execution errors with a high probability. Therefore, we use arithmetic AN-, ANB-, ANBD-, and ANBDmem-codes. These codes detect errors that modify data during storage or transport and errors that disturb computations as well. Furthermore, the error detection provided is independent of the hardware used. We present the following novel encoding approaches: • Software Encoded Processing (SEP) that transforms an unsafe binary into a safe execution at runtime by applying an ANB-code, and • Compiler Encoded Processing (CEP) that applies encoding at compile time and provides different levels of safety by using different arithmetic codes. In contrast to existing encoding solutions, SEP and CEP allow to encode applications whose data and control flow is not completely predictable at compile time. For encoding, SEP and CEP use our set of encoded operations also presented in this thesis. To the best of our knowledge, we are the first ones that present the encoding of a complete RISC instruction set including boolean and bitwise logical operations, casts, unaligned loads and stores, shifts and arithmetic operations. Our evaluations show that encoding with SEP and CEP significantly reduces the amount of erroneous output caused by hardware errors. Furthermore, our evaluations show that, in contrast to replication-based approaches for detecting errors, arithmetic encoding facilitates the detection of permanent hardware errors. This increased reliability does not come for free. However, unexpectedly the runtime costs for the different arithmetic codes supported by CEP compared to redundancy increase only linearly, while the gained safety increases exponentially.

https://tud.qucosa.de/api/qucosa%3A25596/attachment/ATT-0/

Hardware Error Detection Using AN-Codes

Processor cores embedded in systems-on-a-chip (SoCs) are often deployed in critical computations, and when affected by faults they may produce dramatic effects. When hardware hardening is not cost-effective, software implemented hardware fault tolerance (SIHFT) can be a solution to increase SoCs' dependability, but it increases the time for running the hardened application, as well as the memory occupation. In this paper we propose a method that eliminates the memory overhead, by exploiting a new approach to instruction hardening and control flow checking. The proposed method hardens an application online during its execution, without the need for introducing any change in its source code, and is non-intrusive, since it does not require any modification in the main processor's architecture. The method has been tested with two widely used architectures: a microcontroller and a RISC processor, and proven to be suitable for hardening SoCs against transient faults and also for detecting permanent faults.

Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs

Device scaling in new and future technologies brings along severe increase in the soft error rate of circuits, for combinational and sequential logic. Although potential solutions have started to be investigated by the community, the full use of future resources in circuits tolerant to SETs, without performance, area or power penalties, is still an open research issue. This paper introduces MemProc, an embedded core processor with extra low SER sensitivity, and with no performance or area penalty when compared to its RISC counterpart. Central to the SER reduction are the use of new magnetic memories (MRAM and FRAM) and the minimization of the combinational logic area in the core. This paper shows the results of fault injection in the MemProc core processor and in a RISC machine, and compares performance and area of both approaches. Experimental results show a 29 times increase in fault tolerance, with up to 3.75 times in performance gains and 14 times less sensible area.

/pdf/a-low-ser-efficient-core-processor-architecture-for-future-2znz1s2od8.pdf

A low-SER efficient core processor architecture for future technologies

Field Programmable Gate Arrays offer flexibility to program hardware systems together with the possibility to explore any level of parallelism available in the application. Unfortunately, this flexibility costs a huge amount of circuit area necessary to implement all the routing switches and wires. Also, device scaling in new and future technologies brings along a severe increase in the soft error rate of circuits, for combinational and sequential logic. In order to reduce the impact of the wires and switches and cope with SETs in FPGAs, this work proposes a low power voltage-mode quaternary LUT (QLUT) design that uses quaternary logic to reduce the area spent in switches and routing wires. At the same time, the proposed QLUT provides robustness against SETs. Results show that the fault tolerant QLU There proposed detects all faults that can cause an error with significant less area and less power when comparing to the binary correspondent LUT protected with the DWC technique. In order to evaluate how the proposed QLUT will deal with the process variability of sub 90nm technologies, extensive Monte Carlo simulations were performed and these results are here discussed.

A Low Cost Low Power Quaternary LUT Cell for Fault Tolerant Applications in Future Technologies

Evolutions in process design techniques have allowed the construction of atomic-scale structures like nanowires. These 10nm wires can be used in the construction of regular structures with stochastic assemble, and promise to have up to 2 orders of magnitude greater density when compared to advanced CMOS FPGAs build close to 20nm technology. On the other hand, cost-effective fabrication of nanowires demands a bottom-up approach. In other to characterize the wires, the present wire-by-wire test procedure calls for long test time due to the high number of wires that have to be tested. This way, this paper revises some test strategies and characterization procedures for nanowires imposed by the bottom-up approach, and proposes a new approach, based on the number of wires required to build logic gates and the component granularity in the final circuit to reduce the test and characterization time. Results show meaningful reduction of the test and characterization time when comparing the proposed approach with the wire-to-wire granularity approach. The work here presented proposes a new paradigm of test that bypasses the test and characterization procedures and goes right trough the programming phase. The test at the gate level is performed only after the programming phase We compare our results with the theoretical minimum that could be achieved for XOR gates.

Eduardo Luis Rhod

Papers

Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs

A low-SER efficient core processor architecture for future technologies

A Low Cost Low Power Quaternary LUT Cell for Fault Tolerant Applications in Future Technologies

An efficient test and characterization approach for nanowire-based architectures

SW-Based Fault Handling Mechanisms to Cope with EMI in Embedded Electronics: are they a good remedy? A Case Study on a COTS Microprocessor