https://www.cs.montana.edu/courses/csci566/Ref/WMSN-Survey.pdf

A survey on wireless multimedia sensor networks

As new fabrication and integration technologies reduce the cost and size of micro-sensors and wireless interfaces, it becomes feasible to deploy densely distributed wireless networks of sensors and actuators. These systems promise to revolutionize biological, earth, and environmental monitoring applications, providing data at granularities unrealizable by other means. In addition to the challenges of miniaturization, new system architectures and new network algorithms must be developed to transform the vast quantity of raw sensor data into a manageable stream of high-level data. To address this, we propose a tiered system architecture in which data collected at numerous, inexpensive sensor nodes is filtered by local processing on its way through to larger, more capable and more expensive nodes.We briefly describe Habitat monitoring as our motivating application and introduce initial system building blocks designed to support this application. The remainder of the paper presents details of our experimental platform.

Habitat monitoring: Application driver for wireless communications technology

Operation in the subthreshold region most often is synonymous to minimum-energy operation. Yet, the penalty in performance is huge. In this paper, we explore how design in the moderate inversion region helps to recover some of that lost performance, while staying quite close to the minimum-energy point. An energy-delay modeling framework that extends over the weak, moderate, and strong inversion regions is developed. The impact of activity and design parameters such as supply voltage and transistor sizing on the energy and performance in this operational region is derived. The quantitative benefits of operating in near-threshold region are established using some simple examples. The paper shows that a 20% increase in energy from the minimum-energy point gives back ten times in performance. Based on these observations, a pass-transistor based logic family that excels in this operational region is introduced. The logic family operates most of its logic in the above-threshold mode (using low-threshold transistors), yet containing leakage to only those in subthreshold. Operation below minimum-energy point of CMOS is demonstrated. In leakage-dominated ultralow-power designs, time-multiplexing will be shown to yield not only area, but also energy reduction due to lower leakage. Finally, the paper demonstrates the use of ultralow-power design techniques in chip synthesis.

/pdf/ultralow-power-design-in-near-threshold-region-37ua2hp61u.pdf

Ultralow-Power Design in Near-Threshold Region

https://ir.nctu.edu.tw:443/bitstream/11536/15393/1/000299669400001.pdf

Review: From wireless sensor networks towards cyber physical systems

A mechanistic model for out-of-order superscalar processors is developed and then applied to the study of microarchitecture resource scaling. The model divides execution time into intervals separated by disruptive miss events such as branch mispredictions and cache misses. Each type of miss event results in characterizable performance behavior for the execution time interval. By considering an interval's type and length (measured in instructions), execution time can be predicted for the interval. Overall execution time is then determined by aggregating the execution time over all intervals. The mechanistic model provides several advantages over prior modeling approaches, and, when estimating performance, it differs from detailed simulation of a 4-wide out-of-order processor by an average of 7p.The mechanistic model is applied to the general problem of resource scaling in out-of-order superscalar processors. First, we use the model to determine size relationships among microarchitecture structures in a balanced processor design. Second, we use the mechanistic model to study scaling of both pipeline depth and width in balanced processor designs. We corroborate previous results in this area and provide new results. For example, we show that at optimal design points, the pipeline depth times the square root of the processor width is nearly constant. Finally, we consider the behavior of unbalanced, overprovisioned processor designs based on insight gained from the mechanistic model. We show that in certain situations an overprovisioned processor may lead to improved overall performance. Designs where a processor's dispatch width is wider than its issue width are of particular interest.

https://biblio.ugent.be/publication/2093763/file/2093773.pdf

A mechanistic performance model for superscalar out-of-order processors

Method, apparatus, system and machine-readable storage medium for packed data operation mask comparison

A processor includes an execution unit, a fault mask coupled to the execution unit, and a suppress mask coupled to the execution unit. The fault mask is to store a first plurality of bit values to indicate which elements of a multi-element vector have an associated fault generated in response to execution of an instruction on the element in the execution unit. The suppress mask is to store a second plurality of bit values to indicate which of the elements are to have an associated fault suppressed. The processor also includes counter logic to increment a counter in response to an indication of a first fault associated with the first element and received from the fault mask, and an indication of a first suppression associated with the first element and received from the suppress mask. Other embodiments are described as claimed.

Apparatus And Method To Obtain Information Regarding Suppressed Faults

An apparatus and method for performing a variable mask-vector expand. For example, one embodiment of a processor comprises: a source mask register to store a plurality of mask bit values; an index register to store a plurality of index values each associated with a vector data element in a destination vector register and identifying a bit within the source mask register; and variable mask-vector expand logic to expand each of the mask bit values from the source mask register into the associated vector data elements using the index values from the index register, wherein all bits of a vector data element are to be set equal to the mask bit value identified by the index value associated with that vector data element.

Method and apparatus for variably expanding between mask and vector registers

An embodiment of a graphics apparatus may include a context engine to determine contextual information, a recommendation engine communicatively coupled to the context engine to determine a recommendation based on the contextual information, and a configuration engine communicatively coupled to the recommendation engine to adjust a configuration of a graphics operation based on the recommendation. Other embodiments are disclosed and claimed.

Contextual configuration adjuster for graphics

An apparatus and method are described for performing a bit reversal and permutation on mask values. For example, a processor is described to execute an instruction to perform the operations of: reading a plurality of mask bits stored in a source mask register, the mask bits associated with vector data elements of a vector register; and performing a bit reversal operation to copy each mask bit from a source mask register to a destination mask register, wherein the bit reversal operation causes bits from the source mask register to be reversed within the destination mask register resulting in a symmetric, mirror image of the original bit arrangement.

Elmoustapha Ould-Ahmed-Vall

Papers

Method, apparatus, system and machine-readable storage medium for packed data operation mask comparison

Apparatus And Method To Obtain Information Regarding Suppressed Faults

Method and apparatus for variably expanding between mask and vector registers

Contextual configuration adjuster for graphics

Apparatus and method to reverse and permute bits in a mask register