Elmoustapha Ould-Ahmed-Vall

TL;DR: In this paper, the authors present an embodiment of an apparatus for compression of untyped data including a graphical processing unit (GPU) including a data compression pipeline, the data pipeline includes a data port coupled with one or more shader cores.

TL;DR: In this paper, a multi-dimensional loop counter update instruction with a decode logic and an execution logic are presented. And methods to collapse loops using such instructions are described and claimed.

TL;DR: In this paper, a neural network and an arithmetic logic unit including a barrel shifter, an adder, and an accumulator register are used to decode a single instruction into a decoded instruction that specifies multiple operands including an input value and a quantized weight value.

TL;DR: In this article, the authors present an accelerator module comprising a memory stack including multiple memory dies, a graphics processing unit (GPU) coupled with the memory stack via one or more memory controllers, the GPU including a plurality of multiprocessors having a single instruction, multiple thread (SIMT) architecture, and the at least one single instruction to cause at least a portion of the GPU to perform a floating-point operation on input having differing precisions.

TL;DR: In this article, a single mask bit compression instruction that includes a source writemask register operand, a destination writeemask operand and an opcode is described. But it does not specify a single opcode.