https://www.cs.montana.edu/courses/csci566/Ref/WMSN-Survey.pdf

A survey on wireless multimedia sensor networks

As new fabrication and integration technologies reduce the cost and size of micro-sensors and wireless interfaces, it becomes feasible to deploy densely distributed wireless networks of sensors and actuators. These systems promise to revolutionize biological, earth, and environmental monitoring applications, providing data at granularities unrealizable by other means. In addition to the challenges of miniaturization, new system architectures and new network algorithms must be developed to transform the vast quantity of raw sensor data into a manageable stream of high-level data. To address this, we propose a tiered system architecture in which data collected at numerous, inexpensive sensor nodes is filtered by local processing on its way through to larger, more capable and more expensive nodes.We briefly describe Habitat monitoring as our motivating application and introduce initial system building blocks designed to support this application. The remainder of the paper presents details of our experimental platform.

Habitat monitoring: Application driver for wireless communications technology

Operation in the subthreshold region most often is synonymous to minimum-energy operation. Yet, the penalty in performance is huge. In this paper, we explore how design in the moderate inversion region helps to recover some of that lost performance, while staying quite close to the minimum-energy point. An energy-delay modeling framework that extends over the weak, moderate, and strong inversion regions is developed. The impact of activity and design parameters such as supply voltage and transistor sizing on the energy and performance in this operational region is derived. The quantitative benefits of operating in near-threshold region are established using some simple examples. The paper shows that a 20% increase in energy from the minimum-energy point gives back ten times in performance. Based on these observations, a pass-transistor based logic family that excels in this operational region is introduced. The logic family operates most of its logic in the above-threshold mode (using low-threshold transistors), yet containing leakage to only those in subthreshold. Operation below minimum-energy point of CMOS is demonstrated. In leakage-dominated ultralow-power designs, time-multiplexing will be shown to yield not only area, but also energy reduction due to lower leakage. Finally, the paper demonstrates the use of ultralow-power design techniques in chip synthesis.

/pdf/ultralow-power-design-in-near-threshold-region-37ua2hp61u.pdf

Ultralow-Power Design in Near-Threshold Region

https://ir.nctu.edu.tw:443/bitstream/11536/15393/1/000299669400001.pdf

Review: From wireless sensor networks towards cyber physical systems

A mechanistic model for out-of-order superscalar processors is developed and then applied to the study of microarchitecture resource scaling. The model divides execution time into intervals separated by disruptive miss events such as branch mispredictions and cache misses. Each type of miss event results in characterizable performance behavior for the execution time interval. By considering an interval's type and length (measured in instructions), execution time can be predicted for the interval. Overall execution time is then determined by aggregating the execution time over all intervals. The mechanistic model provides several advantages over prior modeling approaches, and, when estimating performance, it differs from detailed simulation of a 4-wide out-of-order processor by an average of 7p.The mechanistic model is applied to the general problem of resource scaling in out-of-order superscalar processors. First, we use the model to determine size relationships among microarchitecture structures in a balanced processor design. Second, we use the mechanistic model to study scaling of both pipeline depth and width in balanced processor designs. We corroborate previous results in this area and provide new results. For example, we show that at optimal design points, the pipeline depth times the square root of the processor width is nearly constant. Finally, we consider the behavior of unbalanced, overprovisioned processor designs based on insight gained from the mechanistic model. We show that in certain situations an overprovisioned processor may lead to improved overall performance. Designs where a processor's dispatch width is wider than its issue width are of particular interest.

https://biblio.ugent.be/publication/2093763/file/2093773.pdf

A mechanistic performance model for superscalar out-of-order processors

PROBLEM TO BE SOLVED: To provide vector scatter operation functionality and/or vector gather operation functionality.SOLUTION: In response to an instruction specifying a gather operation, a destination register, an operand register and a memory address, execution units read values in a mask register, where fields in the mask register correspond to offset indices in an index register for data elements in memory. A first mask value indicates that the element has not been gathered from the memory, and a second value indicates that the element does not need to be, or has already been gathered. Each data element having the first value is gathered from the memory into a destination register location, and a value in the mask register is changed to the second value. When all mask register fields have the second value, a second operation is performed using data in the destination and operand registers.SELECTED DRAWING: Figure 14

Instruction and logic to provide vector scatter operation functionality and vector gather operation functionality

Disclosed embodiments relate to executing a vector multiplication instruction. In one example, a processor includes fetch circuitry to fetch the vector multiplication instruction having fields for an opcode, first and second source identifiers, and a destination identifier, decode circuitry to decode the fetched instruction, execution circuitry to, on each of a plurality of corresponding pairs of fixed-sized elements of the identified first and second sources, execute the decoded instruction to generate a double-sized product of each pair of fixed-sized elements, the double-sized product being represented by at least twice a number of bits of the fixed size, and generate a signed fixed-sized result by rounding the most significant fixed-sized portion of the double-sized product to fit into the identified destination.

Instructions for vector multiplication of signed words with rounding

Computer-implemented method, computer-readable storage medium and apparatus for optimizing codes

Disclosed embodiments relate to instructions for fast element unpacking. In one example, a processor includes fetch circuitry to fetch an instruction whose format includes fields to specify an opcode and locations of an Array-of-Structures (AOS) source matrix and one or more Structure of Arrays (SOA) destination matrices, wherein: the specified opcode calls for unpacking elements of the specified AOS source matrix into the specified Structure of Arrays (SOA) destination matrices, the AOS source matrix is to contain N structures each containing K elements of different types, with same-typed elements in consecutive structures separated by a stride, the SOA destination matrices together contain K segregated groups, each containing N same-typed elements, decode circuitry to decode the fetched instruction, and execution circuitry, responsive to the decoded instruction, to unpack each element of the specified AOS matrix into one of the K element types of the one or more SOA matrices.

Systems for performing instructions for fast element unpacking into 2-dimensional registers

Vector instruction 1401 comprises vector source1420 and destination 1440, destination offset 1430, and mask 1410. Data fields in the mask correspond to locations in the vector. An execution unit copies unmasked vector elements from source operand 1420 to adjacent sequential element locations in the vector destination (e.g. 4 to 7), starting at the offset location. Mask values track progress and/or completion of vector compress and rotate instructions in a processor. Upon copying an unmasked vector source to destination, the corresponding field in the mask is changed to masked. An instruction can be re-executed after the destination, which has become full, is stored to a memory by using the modified mask and an offset of zero. This compresses only the elements that still need execution. Uses include SIMD vector compress and rotate instructions for benchmark applications, e.g. the inner loop of 444.NAMD of the SPEC suite, otherwise not easily vectorised.

Elmoustapha Ould-Ahmed-Vall

Papers

Instruction and logic to provide vector scatter operation functionality and vector gather operation functionality

Instructions for vector multiplication of signed words with rounding

Computer-implemented method, computer-readable storage medium and apparatus for optimizing codes

Systems for performing instructions for fast element unpacking into 2-dimensional registers

Masking for compress and rotate instructions in vector processors