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Enrique Alvarez-Fontecilla
Researcher at University of California, San Diego
Publications - 11
Citations - 70
Enrique Alvarez-Fontecilla is an academic researcher from University of California, San Diego. The author has contributed to research in topics: Phase-locked loop & Biosensor. The author has an hindex of 4, co-authored 11 publications receiving 44 citations. Previous affiliations of Enrique Alvarez-Fontecilla include Analog Devices & Pontifical Catholic University of Chile.
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High-Density Redox Amplified Coulostatic Discharge-Based Biosensor Array
TL;DR: A high-density 4,096-pixel electrochemical biosensor array in 180-nm CMOS using a coulostatic discharge sensing technique and interdigitated electrode (IDE) geometry to reduce both the complexity and size of the readout circuitry is presented.
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Optimal CCD readout by digital correlated double sampling
Cristobal Alessandri,Cristobal Alessandri,Angel Abusleme,Dani Guzman,Ignacio Passalacqua,Enrique Alvarez-Fontecilla,Enrique Alvarez-Fontecilla,Marcelo Guarini +7 more
TL;DR: A theoretical analysis of a generic DCDS readout system is presented, including key aspects such as the signal conditioning stage, the ADC resolution, the sampling frequency and the digital filter implementation, and an accurate, closed-form expression for the signal-to-noise ratio is reached.
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A Time Amplifier Assisted Frequency-to-Digital Converter Based Digital Fractional- N PLL
TL;DR: A wide input-range delay chain based time amplifier and its application to a 6.5-GHz digital fractional-N phase-locked loop (PLL), which includes a delay-averaging linearity enhancement technique and is based on an improved dual-mode ring oscillator (DMRO) frequency-to-digital converter (FDC).
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Canonical Syllogistic Moods in Traditional Aristotelian Logic
TL;DR: This paper presents an overview of the recently proposed theoretical formulation of Categorical Logic, along with the derivation of the 48 canonical syllogistic moods that are capable of generating the 3072 conclusive moods previously reported.
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Delta-Sigma FDC Enhancements for FDC-Based Digital Fractional- N PLLs
TL;DR: In this paper, the authors describe all-digital enhancements for digital fractional-nodes phase-locked loops (PLLs) based on delta-sigma frequency-to-digital converters (FDCs).