Model Checking

From the Publisher:
This work covers all aspects of physical design. The book is a core reference for graduate students and CAD professionals. For students, concept and algorithms are presented in an intuitive manner. For CAD professionals, the material presents a balance of theory and practice. An extensive bibliography is provided which is useful for finding advanced material on a topic. At the end of each chapter, exercises are provided, which range in complexity from simple to research level.

Algorithms for VLSI Physical Design Automation

This survey presents an overview of recent advances in the state of the art for computer-aided design (CAD) tools for analog and mixed-signal integrated circuits (ICs). Analog blocks typically constitute only a small fraction of the components on mixed-signal ICs and emerging systems-on-a-chip (SoC) designs. But due to the increasing levels of integration available in silicon technology and the growing requirement for digital systems to communicate with the continuous-valued external world, there is a growing need for CAD tools that increase the design productivity and improve the quality of analog integrated circuits. This paper describes the motivation and evolution of these tools and outlines progress on the various design problems involved: simulation and modeling, symbolic analysis, synthesis and optimization, layout generation, yield analysis and design centering, and test. This paper summarizes the problems for which viable solutions are emerging and those which are still unsolved.

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Computer-aided design of analog and mixed-signal integrated circuits

In practice, finite state concurrent systems often exhibit considerable symmetry. We investigate techniques for reducing the complexity of temporal logic model checking in the presence of symmetry. In particular, we show that symmetry can frequently be used to reduce the size of the state space that must be explored during model checking. In the past, symmetry has been exploited in computing the set of reachable states of a system when the transition relation is represented explicitly [13, 10, 17]. However, this research did not consider arbitrary temporal properties or the complications that arise when BDDs are used in such procedures. We have formalized what it means for a finite state system to be symmetric and described techniques for reducing such systems when the transition relation is given explicitly in terms of states or symbolically as a BDD. Moreover, we have identified an important class of temporal logic formulas that are preserved ander this reduction. Our paper also investigates the complexity of various critical steps, like the computation of the orbit relation, which arise when symmetry is used in this type of verification. Finally, we have tested our ideas on a simple cache-coherency protocol based on the IEEE Futurebus+ standard.

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Exploiting Symmetry In Temporal Logic Model Checking

Traditionally, work on analog testing has focused on diagnosing faults in board designs. Recently, with increasing levels of integration, not just diagnosing faults, but distinguishing between faulty and good circuits has become a problem. Analog blocks embedded in digital systems may not easily be separately testable. Consequently, many papers have been recently written proposing techniques to reduce the burden of testing analog and mined-signal circuits. This survey attempts to outline some of this recent work, ranging from tools for simulation-based test set development and optimization to built-in self-test (BIST) circuitry.

A tutorial introduction to research on analog and mixed-signal circuit testing

A methodology for hierarchical statistical circuit characterization which does not rely upon circuit-level Monte Carlo simulation is presented. The methodology uses principal component analysis, response surface methodology, and statistics to directly calculate the statistical distributions of higher-level parameters from the distributions of lower-level parameters. We have used the methodology to characterize a folded cascode operational amplifier and a phase-locked loop. This methodology permits the statistical characterization of large analog and mixed-signal systems, many of which are extremely time-consuming or impossible to characterize using existing methods.

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Hierarchical statistical characterization of mixed-signal circuits using behavioral modeling

Binary Decision Diagrams (BDDs) are a data structure frequently used to represent complex Boolean functions in formal verification algorithms. An efficient heuristic algorithm for dynamically reducing the size of large reduced ordered BDDs by optimally reordering small windows of consecutive variables is presented. The algorithms have been fully integrated into the Berkeley and Carnegie Mellon BDD packages in such a way that the current variable order dynamically changes and is completely transparent to the user. Dynamic reordering significantly reduces the memory required for BDD-based verification algorithms, thus permitting the verification of significantly more complex systems than was previously possible. The algorithms exhibit a smooth tradeoff between CPU time and reduction in BDD size for almost all BDDs tested. >

Dynamic variable reordering for BDD minimization

This paper presents a new methodology for measuring MOS transistor current mismatch and a new transistor current mismatch model The new methodology is based on extracting the mismatch information from a fully functional circuit rather than on probing individual devices; this extraction leads to more efficient and more accurate mismatch measurement The new model characterizes the total mismatch as a sum of two components, one systematic and the other random For our process, we attribute nearly half of the mismatch to the systematic component, which we model as a linear gradient across the die Furthermore, we present a new model for the random component of the mismatch which is 60% more accurate, on average, than existing models

/pdf/measurement-and-modeling-of-mos-transistor-current-mismatch-20f2igjoxv.pdf

Measurement and modeling of MOS transistor current mismatch in analog IC's

This paper presents an efficient strategy for testability analysis and fault diagnosis of analog circuits using behavioral models. A key contribution is a new algorithm for determining analog testability. Experimentally, we determined the testability and faults of a fabricated 10 bit digital-to-analog converter modeled using the analog hardware description language, Cadence-AHDL. Also, we applied the testability analysis at the circuit level using SPICE sensitivity analysis. >

Analog testability analysis and fault diagnosis using behavioral modeling

To accelerate the design cycle for analog circuits and mixed-signal systems, we have proposed a top-down, constraint-driven design methodology. In this paper we present a design which demonstrates the two principal advantages that this methodology provides- a high probability for first silicon which meets all specifications and fast design times. We examine the design of three different 10-bit digital-to-analog (D/A) converters beginning from their performance and functional specifications and ending with the testing of the fabricated parts. Critical technology mismatch information gathered from the testing phase is provided. >

Eric Felt

Papers

Hierarchical statistical characterization of mixed-signal circuits using behavioral modeling

Dynamic variable reordering for BDD minimization

Measurement and modeling of MOS transistor current mismatch in analog IC's

Analog testability analysis and fault diagnosis using behavioral modeling

Top-down, constraint-driven design methodology based generation of n-bit interpolative current source D/A converters