E
Eric Felt
Researcher at University of California, Berkeley
Publications - 12
Citations - 328
Eric Felt is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: Design methods & Physical design. The author has an hindex of 10, co-authored 12 publications receiving 325 citations.
Papers
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Proceedings ArticleDOI
Hierarchical statistical characterization of mixed-signal circuits using behavioral modeling
TL;DR: A methodology for hierarchical statistical circuit characterization which does not rely upon circuit-level Monte Carlo simulation is presented and permits the statistical characterization of large analog and mixed-signal systems.
Proceedings ArticleDOI
Dynamic variable reordering for BDD minimization
TL;DR: An efficient heuristic algorithm for dynamically reducing the size of large reduced ordered BDDs by optimally reordering small windows of consecutive variables is presented.
Proceedings ArticleDOI
Measurement and modeling of MOS transistor current mismatch in analog IC's
TL;DR: The new methodology is based on extracting the mismatch information from a fully functional circuit rather than on probing individual devices; this extraction leads to more efficient and more accurate mismatch measurement.
Proceedings ArticleDOI
Analog testability analysis and fault diagnosis using behavioral modeling
TL;DR: This paper presents an efficient strategy for testability analysis and fault diagnosis of analog circuits using behavioral models and develops a new algorithm for determining analog testability.
Proceedings ArticleDOI
Top-down, constraint-driven design methodology based generation of n-bit interpolative current source D/A converters
Henry Chang,E. Liu,R. Neff,Eric Felt,E. Malavasi,Edoardo Charbon,Alberto Sangiovanni-Vincentelli,Paul R. Gray +7 more
TL;DR: In this article, a top-down, constraint-driven design methodology is proposed to accelerate the design cycle for analog circuits and mixed-signal systems, and a design which demonstrates the two principal advantages that this methodology provides-a high probability for first silicon which meets all specifications and fast design times.