High-performance top-gated carbon nanotube field-effect transistors (CNT FETs) with a gate length of 5 nanometers can be fabricated that perform better than silicon complementary metal-oxide semiconductor (CMOS) FETs at the same scale. A scaling trend study revealed that the scaled CNT-based devices, which use graphene contacts, can operate much faster and at much lower supply voltage (0.4 versus 0.7 volts) and with much smaller subthreshold slope (typically 73 millivolts per decade). The 5-nanometer CNT FETs approached the quantum limit of FETs by using only one electron per switching operation. In addition, the contact length of the CNT CMOS devices was also scaled down to 25 nanometers, and a CMOS inverter with a total pitch size of 240 nanometers was also demonstrated.

http://science.sciencemag.org/content/sci/355/6322/271.full.pdf

Scaling carbon nanotube complementary transistors to 5-nm gate lengths

This paper presents a programmable and scalable digital neuromorphic architecture based on 3D high-density memory integrated with logic tier for efficient neural computing. The proposed architecture consists of clusters of processing engines, connected by 2D mesh network as a processing tier, which is integrated in 3D with multiple tiers of DRAM. The PE clusters access multiple memory channels (vaults) in parallel. The operating principle, referred to as the memory centric computing, embeds specialized state-machines within the vault controllers of HMC to drive data into the PE clusters. The paper presents the basic architecture of the Neurocube and an analysis of the logic tier synthesized in 28nm and 15nm process technologies. The performance of the Neurocube is evaluated and illustrated through the mapping of a Convolutional Neural Network and estimating the subsequent power and performance for both training and inference.

Neurocube: a programmable digital neuromorphic architecture with high-density 3D memory

Within-die parameter variation poses a major challenge to high-performance microprocessor design, negatively impacting a processor's frequency and leakage power. Addressing this problem, this paper proposes a microarchitecture-aware model for process variation-including both random and systematic effects. The model is specified using a small number of highly intuitive parameters. Using the variation model, this paper also proposes a framework to model timing errors caused by parameter variation. The model yields the failure rate of microarchitectural blocks as a function of clock frequency and the amount of variation. With the combination of the variation model and the error model, we have VARIUS, a comprehensive model that is capable of producing detailed statistics of timing errors as a function of different process parameters and operating conditions. We propose possible applications of VARIUS to microarchitectural research.

/pdf/varius-a-model-of-process-variation-and-resulting-timing-4ybc28o8ss.pdf

VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects

The scaling of transistors to sub-10 nm dimensions is strongly limited by their contact resistance (RC). Here we present a systematic study of scaling MoS2 devices and contacts with varying electrode metals and controlled deposition conditions, over a wide range of temperatures (80 to 500 K), carrier densities (1012 to 1013 cm–2), and contact dimensions (20 to 500 nm). We uncover that Au deposited in ultra-high vacuum (∼10–9 Torr) yields three times lower RC than under normal conditions, reaching 740 Ω·μm and specific contact resistivity 3 × 10–7 Ω·cm2, stable for over four months. Modeling reveals separate RC contributions from the Schottky barrier and the series access resistance, providing key insights on how to further improve scaling of MoS2 contacts and transistor dimensions. The contact transfer length is ∼35 nm at 300 K, which is verified experimentally using devices with 20 nm contacts and 70 nm contact pitch (CP), equivalent to the “14 nm” technology node.

Improved Contacts to MoS2 Transistors by Ultra-High Vacuum Metal Deposition

In the past five decades, the semiconductor industry has gone through two distinct eras of scaling: the geometric (or classical) scaling era and the equivalent (or effective) scaling era. As transistor and memory features approach 10 nanometres, it is apparent that room for further scaling in the horizontal direction is running out. In addition, the rise of data abundant computing is exacerbating the interconnect bottleneck that exists in conventional computing architecture between the compute cores and the memory blocks. Here we argue that electronics is poised to enter a new, third era of scaling — hyper-scaling — in which resources are added when needed to meet the demands of data abundant workloads. This era will be driven by advances in beyond-Boltzmann transistors, embedded non-volatile memories, monolithic three-dimensional integration and heterogeneous integration techniques. This Perspective argues that electronics is poised to enter a new era of scaling – hyper-scaling – driven by advances in beyond-Boltzmann transistors, embedded non-volatile memories, monolithic three-dimensional integration, and heterogeneous integration techniques.

The era of hyper-scaling in electronics

Described is an apparatus which comprises: a memory; a first power supply node to receive a first power supply; a second power supply node coupled to the memory to provide the memory with second power supply; a circuit coupled to the first and second power supply nodes, the circuit operable to dynamically modulate droop in the second power supply by adaptively adjusting signal characteristics of a write assist pulse.

Apparatus for adaptive write assist for memory

This paper presents the recent mmWave and sub-THz oriented technology developments as part of RF design-technology co-optimization (DTCO) efforts in Intel 22nm FinFET process (22FFL). Several back-end-of-line (BEOL) and front-end-of-line (FEOL) improvements have been implemented for high frequency applications. In the newly developed BEOL, ExpressVia is introduced, which allows direct transistor connection to thick metal. Continuous via and 3+1 thick metal layers are enabled for design flexibility. The high performance RF transistor (RF HP) is optimized with the new BEOL and characterized at top metal. Additional process improvements in high power RF device (HyPowerFF) and varactors are also implemented. These BEOL and FEOL improvements enable high performance, innovative mmWave and sub-THz circuits and systems.

mmWave and sub-THz Technology Development in Intel 22nm FinFET (22FFL) Process

Memory bit cells having internal node jumpers are described. In an example, an integrated circuit structure includes a memory bit cell on a substrate. The memory bit cell includes first and second gate lines parallel along a second direction of the substrate. The first and second gate lines have a first pitch along a first direction of the substrate, the first direction perpendicular to the second direction. First, second and third interconnect lines are over the first and second gate lines. The first, second and third interconnect lines are parallel along the second direction of the substrate. The first, second and third interconnect lines have a second pitch along the first direction, where the second pitch is less than the first pitch. One of the first, second and third interconnect lines is an internal node jumper for the memory bit cell.

Internal node jumper for memory bit cells

A 21-Mb/mm2 SRAM design using 0.0367- $\mu {\mathrm{ m}}^{2}$ HCC bitcell on a 10-nm CMOS technology is presented. Gate-modulated self-collapse (GSC) write-assist is utilized to enable 175 mV $V_{\mathrm{ MIN}}$ reduction with negligible active energy overhead, and a modest 5.5% array area overhead on a 256-Kb instance. Compared to NBL and TVC write-assist techniques, GSC delivers comparable $V_{\mathrm{ MIN}}$ improvement across a wide frequency range with 31%–108% write energy reduction.

10-nm SRAM Design Using Gate-Modulated Self-Collapse Write-Assist Enabling 175-mV V MIN Reduction With Negligible Active Power Overhead

A static random-access memory is described. The SRAM includes a storage cell and a voltage supply to supply the storage cell with a reduced voltage during a write operation. The SRAM cell includes a first pass gate and a second pass gate. A first resistor is coupled between the first pass gate and a first side of the storage cell. A second resistor is coupled between the second pass gate and a second side of the storage cell.

Eric Karl

Papers

Apparatus for adaptive write assist for memory

mmWave and sub-THz Technology Development in Intel 22nm FinFET (22FFL) Process

Internal node jumper for memory bit cells

10-nm SRAM Design Using Gate-Modulated Self-Collapse Write-Assist Enabling 175-mV V MIN Reduction With Negligible Active Power Overhead

Operation aware auto-feedback sram