Steep subthreshold swing transistors based on interband tunneling are examined toward extending the performance of electronics systems. In particular, this review introduces and summarizes progress in the development of the tunnel field-effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges. The promise of the TFET is in its ability to provide higher drive current than the MOSFET as supply voltages approach 0.1 V.

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Low-Voltage Tunnel Transistors for Beyond CMOS Logic

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

This review paper explores considerations for ultimate CMOS transistor scaling Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted Key technology challenges (such as advanced gate stacks, mobility, resistance, and capacitance) shared by all of the architectures will be discussed in relation to recent research results

Considerations for Ultimate CMOS Scaling

A lithographic apparatus configured to project a patterned beam of radiation onto a target portion of a substrate is disclosed. The apparatus includes a first radiation dose detector and a second radiation dose detector, each detector comprising a secondary electron emission surface configured to receive a radiation flux and to emit secondary electrons due to the receipt of the radiation flux, the first radiation dose detector located upstream with respect to the second radiation dose detector viewed with respect to a direction of radiation transmission, and a meter, connected to each detector, to detect a current or voltage resulting from the secondary electron emission from the respective electron emission surface.

Lithographic apparatus, and device manufacturing method

A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.

System comprising a semiconductor device and structure

Moore's law technology scaling has improved performance by five orders of magnitude in the last four decades. As advanced technologies continue the pursuit of Moore's law, a variety of challenges will need to be overcome. One of these challenges is the management of process variation. This paper discusses the importance of process variation in modern transistor technology, reviews front-end variation sources, presents device and circuit variation measurement techniques, including circuit and memory data from the 32-nm node, and compares recent intrinsic transistor variation performance from the literature.

Process Technology Variation

An apparatus for actuating a droplet comprises a first conductive layer, a second conductive layer, a conductive elongate element, and a voltage source. The first conductive layer comprises a first hydrophobic surface. The second conductive layer comprises a hydrophilic surface facing the first hydrophobic surface. The second conductive layer is axially spaced from the first conductive layer to define a gap therebetween. The conductive medial element is disposed in the gap between the first and second conductive layers, and comprises a second hydrophobic surface. The voltage source communicates with the second conductive layer and the elongate element. By applying a voltage potential between the elongate element and the second conductive layer, droplets can be electrostatically actuated so as to move from the first conductive layer into contact with the second conductive layer. The apparatus is particularly useful in the synthesis of microarrays of biological, chemical, or biochemical samples.

Method and apparatus for non-contact electrostatic actuation of droplets

A leading edge 32nm high-k/metal gate transistor technology has been optimized for SoC platform applications that span a wide range of power, performance, and feature space. This technology has been developed to be modular, offering mix-and-match transistors, interconnects, RF/analog passive elements, embedded memory, and noise mitigation options. The low gate leakage of the high-k gate dielectric enables the triple transistor architecture to support ultra low power, high performance, and high voltage tolerant I/O devices concurrently. Embedded memories include high density (0.148 um2) and low voltage (0.171 um2) SRAMs as well as secure OTP fuses. Analog/RF SoC features include high precision, high quality passives (resistors, capacitors and inductors) and deep-nwell noise isolation.

https://www.intel.com/content/dam/doc/technology-brief/32nm-soc-platform-technology-paper.pdf

A 32nm SoC platform technology with 2 nd generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications

Erratic bit phenomena have been reported in advanced flash memories, and have been attributed to trapping/detrapping effects that modify the threshold voltage This paper describes for the first time the observance of erratic behavior in SRAM Vmin, defined as the minimum voltage at which the SRAM array is functional Random telegraph signal (RTS) noise in the soft breakdown gate leakage is shown to be the cause The erratic Vmin phenomenon can be eliminated for 90 nm SRAMs by process optimization However, erratic Vmin behavior gets worse with smaller cell sizes and represents another constraint on the scaling of SRAM cells and on the minimum operating voltage of the SRAM array A combination of process and circuit solutions will likely be needed to enable continued SRAM cell scaling

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Erratic fluctuations of sram cache vmin at the 90nm process technology node

SRAM scaling faces increasing challenges in meeting power, performance, and density requirements as Moore's law continues to drive CMOS technology scaling. Due to process variation, SRAM bitcell design margin continues to shrink in scaled technologies and conventional SRAM is no longer able to fully realize the benefits of scaling. Smart and adaptive assist circuits can improve design margins while satisfying SRAM power and performance requirements in scaled technologies. VCC scaling is especially important to meet increasingly stringent power constraints [1]. Circuit techniques proposed in recent years enable SRAM V CC scaling by expanding read and write margins [2–6]. However, the improved design margins for SRAM V CC scaling are often achieved with significant design overhead, e.g., additional power supply [4], increased circuit complexity [5], and testing overheads required for die-by-die programming [6].

Pramod Kolar

Papers

Process Technology Variation

Method and apparatus for non-contact electrostatic actuation of droplets

A 32nm SoC platform technology with 2 nd generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications

Erratic fluctuations of sram cache vmin at the 90nm process technology node

A 32 nm High-k Metal Gate SRAM With Adaptive Dynamic Stability Enhancement for Low-Voltage Operation