M
Mark Armstrong
Researcher at Intel
Publications - Â 38
Citations - Â 3997
Mark Armstrong is an academic researcher from Intel. The author has contributed to research in topics: Transistor & PMOS logic. The author has an hindex of 18, co-authored 38 publications receiving 3845 citations.
Papers
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Proceedings ArticleDOI
A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors
Tahir Ghani,Mark Armstrong,C. Auth,M. Bost,P. Charvat,G. Glass,T. Hoffmann,K. Johnson,C. Kenyon,Jason Klaus,B. McIntyre,Kaizad Mistry,Anand Portland Murthy,J. Sandford,M. Silberstein,Swaminathan Sivakumar,Pete Smith,K. Zawadzki,Scott E. Thompson,M. Bohr +19 more
TL;DR: In this article, the authors describe a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers, which features an epitaxially grown strained SiGe film embedded in the source drain regions.
Journal ArticleDOI
A 90-nm logic technology featuring strained-silicon
Scott E. Thompson,Mark Armstrong,C. Auth,Mohsen Alavi,M. Buehler,R. Chau,S. Cea,Tahir Ghani,G. Glass,T. Hoffman,Chia-Hong Jan,C. Kenyon,Jason Klaus,K. Kuhn,Z. Ma,B. McIntyre,Kaizad Mistry,Anand Portland Murthy,B. Obradovic,Ramune Nagisetty,P. Nguyen,Swaminathan Sivakumar,R. Shaheed,Lucian Shifren,B. Tufts,S. Tyagi,M. Bohr,Y. El-Mansy +27 more
TL;DR: In this paper, a leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low/spl kappa/CDO for high-performance dense logic is presented.
Journal ArticleDOI
A logic nanotechnology featuring strained-silicon
Scott E. Thompson,Mark Armstrong,C. Auth,S. Cea,R. Chau,G. Glass,T. Hoffman,Jason Klaus,Z. Ma,B. McIntyre,Anand Portland Murthy,B. Obradovic,Lucian Shifren,Swaminathan Sivakumar,S. Tyagi,Tahir Ghani,Kaizad Mistry,Mark T. Bohr,Y. El-Mansy +18 more
TL;DR: In this article, a tensile Si nitride-capping layer is used to introduce tensile uniaxial strain into the n-type MOSFET and enhance electron mobility.
Proceedings ArticleDOI
A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 /spl mu/m/sup 2/ SRAM cell
Scott E. Thompson,Nidhi Anand,Mark Armstrong,C. Auth,B. Arcot,Mohsen Alavi,P. Bai,J. Bielefeld,Robert M. Bigwood,J. Brandenburg,M. Buehler,Stephen M. Cea,V. Chikarmane,C. H. Choi,R. Frankovic,Tahir Ghani,G. Glass,W. Han,Thomas Hoffmann,Makarem A. Hussein,P. Jacob,Ajay Jain,Chia-Hong Jan,Subhash M. Joshi,C. Kenyon,Jason Klaus,S. Klopcic,J. Luce,Z. Ma,B. McIntyre,Kaizad Mistry,Anand Portland Murthy,P. Nguyen,H. Pearson,T. Sandford,R. Schweinfurth,R. Shaheed,Swaminathan Sivakumar,M. Taylor,B. Tufts,Charles H. Wallace,P.-H. Wang,Cory E. Weber,Mark T. Bohr +43 more
TL;DR: In this paper, a leading edge 90 nm technology with 1.2 nm physical gate oxide, 50 nm gate length, strained silicon, NiSi, 7 layers of Cu interconnects, and low k carbon-doped oxide (CDO) for high performance dense logic is presented.
Journal ArticleDOI
Comparison of Junctionless and Conventional Trigate Transistors With $L_{g}$ Down to 26 nm
Rafael Rios,Annalisa Cappellani,Mark Armstrong,Aaron A. Budrevich,Harry Gomez,R. Pai,Nadia M. Rahhal-Orabi,K. Kuhn +7 more
TL;DR: In this paper, the authors presented the first experimental comparison of short-channel JAM-to-IM devices at matched off-state leakage (Ioff) and showed that the JAM devices showed better channel mobility and lower gate capacitance than the IM control counterparts at matched Ioff.