Spintronics, or spin electronics, involves the study of active control and manipulation of spin degrees of freedom in solid-state systems. This article reviews the current status of this subject, including both recent advances and well-established results. The primary focus is on the basic physical principles underlying the generation of carrier spin polarization, spin dynamics, and spin-polarized transport in semiconductors and metals. Spin transport differs from charge transport in that spin is a nonconserved quantity in solids due to spin-orbit and hyperfine coupling. The authors discuss in detail spin decoherence mechanisms in metals and semiconductors. Various theories of spin injection and spin-polarized transport are applied to hybrid structures relevant to spin-based devices and fundamental studies of materials properties. Experimental work is reviewed with the emphasis on projected applications, in which external electric and magnetic fields and illumination by light will be used to control spin and charge dynamics to create new functionalities not feasible or ineffective with conventional electronics.

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Spintronics: Fundamentals and applications

http://files.janapv.webnode.cz/200000097-8a03f8afdf/ex_bias_nano.pdf

Exchange bias in nanostructures

Materials research has driven the development of modern nano-electronic devices. In particular, research in magnetic thin films has revolutionized the development of spintronic devices1,2 because identifying new magnetic materials is key to better device performance and design. Van der Waals crystals retain their chemical stability and structural integrity down to the monolayer and, being atomically thin, are readily tuned by various kinds of gate modulation3,4. Recent experiments have demonstrated that it is possible to obtain two-dimensional ferromagnetic order in insulating Cr2Ge2Te6 (ref. 5) and CrI3 (ref. 6) at low temperatures. Here we develop a device fabrication technique and isolate monolayers from the layered metallic magnet Fe3GeTe2 to study magnetotransport. We find that the itinerant ferromagnetism persists in Fe3GeTe2 down to the monolayer with an out-of-plane magnetocrystalline anisotropy. The ferromagnetic transition temperature, Tc, is suppressed relative to the bulk Tc of 205 kelvin in pristine Fe3GeTe2 thin flakes. An ionic gate, however, raises Tc to room temperature, much higher than the bulk Tc. The gate-tunable room-temperature ferromagnetism in two-dimensional Fe3GeTe2 opens up opportunities for potential voltage-controlled magnetoelectronics7-11 based on atomically thin van der Waals crystals.

Gate-tunable Room-temperature Ferromagnetism in Two-dimensional Fe 3 GeTe 2

Ordered magnetic nanostructures: fabrication and properties

Recent technological advances in the development of flash-memory based devices have consolidated their leadership position as the preferred storage media in the embedded systems market and opened new vistas for deployment in enterprise-scale storage systems. Unlike hard disks, flash devices are free from any mechanical moving parts, have no seek or rotational delays and consume lower power. However, the internal idiosyncrasies of flash technology make its performance highly dependent on workload characteristics. The poor performance of random writes has been a cause of major concern, which needs to be addressed to better utilize the potential of flash in enterprise-scale environments. We examine one of the important causes of this poor performance: the design of the Flash Translation Layer (FTL), which performs the virtual-to-physical address translations and hides the erase-before-write characteristics of flash. We propose a complete paradigm shift in the design of the core FTL engine from the existing techniques with our Demand-based Flash Translation Layer (DFTL), which selectively caches page-level address mappings. We develop a flash simulation framework called FlashSim. Our experimental evaluation with realistic enterprise-scale workloads endorses the utility of DFTL in enterprise-scale storage systems by demonstrating: (i) improved performance, (ii) reduced garbage collection overhead and (iii) better overload behavior compared to state-of-the-art FTL schemes. For example, a predominantly random-write dominant I/O trace from an OLTP application running at a large financial institution shows a 78% improvement in average response time (due to a 3-fold reduction in operations of the garbage collector), compared to a state-of-the-art FTL scheme. Even for the well-known read-dominant TPC-H benchmark, for which DFTL introduces additional overheads, we improve system response time by 56%.

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DFTL: a flash translation layer employing demand-based selective caching of page-level address mappings

We summarize the features of existing semiconductor memories and compare them to Magnetoresistive Random Access Memory (MRAM),a semiconductor memory with magnetic bits for nonvolatile storage. MRAM architectures based on Giant Magnetoresistance (GMR) and Magnetic Tunnel Junction (MTJ) cells are described. This paper will discuss our progress on improving the material structures, memory bits, thermal stability of the bits, and competitive architectures for GMR and MTJ based MRAM memories as well as the potential of these memories in the commercial memory market.

Progress and outlook for MRAM technology

We summarize our progress on Magnetoresistive Random Access Memory (MRAM) based on Magnetic Tunnel Junctions (MTJ). We have demonstrated MTJ material in the 1-1000 k/spl Omega/-/spl mu/m/sup 2/ range with MR values above 40%. The switching characteristics are mainly governed by the magnetic shape anisotropy that arises from the element boundaries. The switching repeatability, as well as hard axis selectability, are shown to be dependent on both shape and aspect ratio. MTJ memory elements were successfully integrated with 0.6 /spl mu/m CMOS technology, achieving read and program address access times of 14 ns in a 256/spl times/2 MRAM.

Recent developments in magnetic tunnel junction MRAM

Various giant magnetoresistance material structures were patterned and studied for their potential as memory elements. The preferred memory element, based on pseudo-spin valve structures, was designed with two magnetic stacks (NiFeCo/CoFe) of different thickness with Cu as an interlayer. The difference in thickness results in dissimilar switching fields due to the shape anisotropy at deep submicron dimensions. It was found that a lower switching current can be achieved when the bits have a word line that wraps around the bit 1.5 times. Submicron memory elements integrated with complementary metal–oxide–semiconductor (CMOS) transistors maintained their characteristics and no degradation to the CMOS devices was observed. Selectivity between memory elements in high-density arrays was demonstrated.

High density submicron magnetoresistive random access memory (invited)

An improved and novel device and fabrication method for a magnetic element, and more particularly a magnetic element (10) including a first electrode (14), a second electrode (18) and a spacer layer (16). The first electrode (14) includes a fixed ferromagnetic layer (26). A second electrode (18) is included and comprises a free ferromagnetic layer (28). A spacer layer (16) is located between the fixed ferromagnetic layer (26) and the free ferromagnetic (28) layer, the spacer layer (16). At least one additional layer (20 & 22) is provided between the base metal layer (13) and the spacer layer (16). The base metal layer (13) or at least one of the layers positioned between the base metal layer (13) and the spacer layer (16) having an x-ray amorphous structure such that a reduced topological coupling strength between the free ferromagnetic layer (28) and the fixed ferromagnetic layer (26) is achieved.

Magnetic element with improved field response and fabricating method thereof

An improved and novel magnetic element (10; 10'; 50; 50'; 80) including a plurality of thin film layers wherein the bit end magneto-static demagnetizing fields cancel the total positive coupling of the structure to obtain dual magnetic states in a zero external field. Additionally disclosed is a method of fabricating a magnetic element (10) by providing a plurality of thin film layers wherein the bit end magneto-static demagnetizing fields of the thin film layers cancel the total positive coupling of the structure to obtain dual magnetic states in a zero external field.

Eugene Youjun Chen

Papers

Progress and outlook for MRAM technology

Recent developments in magnetic tunnel junction MRAM

High density submicron magnetoresistive random access memory (invited)

Magnetic element with improved field response and fabricating method thereof

Magnetic dual element with dual magnetic states and fabricating method thereof