Flying-adder frequency synthesis architecture is a novel technique of generating frequency on chip. Since its invention, it has been utilized in many commercial products to cope with various difficult challenges. During the evolution of this architecture, the issues related to circuit- and system-level implementation have been studied in prior publications. However, rigorous mathematical treatment on this architecture has not been established. In this paper, we attempt to explore and understand the signal characteristics and frequency domain behavior of this architecture through mathematical analysis. In the meantime, the underlying concept associated with this architecture, time-average-frequency, is formally introduced.

The concept of time-average-frequency and mathematical analysis of flying-adder frequency synthesis architecture

This paper discusses the design and development of a FPGA-based chirp generator for high resolution Unmanned Aerial Vehicle (UAV) Synthetic Aperture Radar. The desired bandwidth of the chirp signal is 100MHz (combination of I and Q channels) with a chirp rate of 5MHz/"s. Two algorithms based on the Memory-based architecture and the Direct Digital Synthesizer (DDS) architecture are presented. The measurement results indicate that the DDS chirp generator is a preferred choice for high-resolution SAR application.

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Fpga-based chirp generator for high resolution uav sar

The main purpose of this paper is to review the framework behind direct digital synthesizer phase-locked loops (DDS-PLLs), as well as to provide a set of novel techniques that can be used during the development and the deployment of phased arrays based on local oscillator (LO) phase shifting approaches. A beam steering transmitter prototype employing our revised DDS-PLL architecture and the experimental results obtained during its characterization are presented. The main contribution of the proposed implementation consists in showing that the output phase increments of the DDS-PLL are unaffected by the frequency multiplication operated by the PLL. The proposed prototype is centered at 3.350 GHz and allows to independently set the phase of its four LOs at 2.453 GHz with an 8-bit resolution. The DDS-PLL architecture is frequency-independent, and the modular structure of its phase control units allows to achieve different phase resolutions with a very small redesign effort.

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DDS-PLL Phase Shifter Architectures for Phased Arrays: Theory and Techniques

A wideband frequency synthesizer architecture is presented. The proposed topology employs a direct digital frequency synthesizer (DDFS) to control the output frequency of an offset-PLL. In this way, the synthesizer features a very fine frequency resolution, 24 Hz, as in delta-sigma fractional-N PLLs, but without being affected by the quantization-induced phase noise. This, in turn, allows enlarging the loop bandwidth. The frequency synthesizer is designed to be employed as a direct modulator for Bluetooth transmitter in a low-cost 0.35-mum CMOS technology. At 2.5GHz it achieves 1.8-MHz bandwidth, while the settling time within 30ppm for an 80-MHz step is 3 mus. The integrated phase noise gives less than 1 degree of rms phase error and the worst-case spur is 48dBc at 1 MHz, well below the specifications. Power dissipation is 120 mW for the PLL core, 50 mW for the DDFS plus DACs, and 19 mW for the GFSK modulator.

A 2.5-GHz DDFS-PLL With 1.8-MHz Bandwidth in 0.35- $\mu$ m CMOS

This paper describes a novel phase-locked loop (PLL) architecture utilizing an optoelectronic oscillator (OEO) as a voltage-controlled oscillator (VCO). The OEO demonstrates excellent far-out phase-noise performance while the PLL reduces the close-in phase noise. The nonmonotonic VCO characteristics of the OEO placed stringent demands on the loop filter electronics and startup conditions. The crystal reference, prescalar, frequency synthesizer, and loop filter were all implemented with discrete high-performance components. The resulting frequency synthesizer yields a $-$ 10-dBm output at 20 GHz with phase noise of $-$ 80 dBc/Hz at 100-Hz offset, and $-$ 134 dBc/Hz at 10-kHz offset. These results are far superior to PLL synthesizers utilizing only an electronic VCO and illustrate the power of optoelectronic integration.

An Ultra-Low Phase-Noise 20-GHz PLL Utilizing an Optoelectronic Voltage-Controlled Oscillator

In this transactions brief, we present a direct digital synthesizer (DDS)-based phase-locked loop (PLL), for frequency synthesis at 2.4 GHz with 80-MHz tuning range. The DDS signal is mixed with the voltage-control oscillator output in the PLL feedback path. This solution helps in avoiding some of the typical tradeoffs in PLL. In particular, it is possible to achieve a very high-frequency resolution together with fast settling and spectral purity. These characteristics are often incompatible both in integer and fractional dividers PLL. A prototype was fabricated on PCBs and tested. The settling time is about 3 /spl mu/s for 0.1 ppm (240 Hz) accuracy. Worst-case spurs are -53 dBc at 8-MHz offset from the carrier. The integrated phase noise in the band 1 kHz -1 MHz is 0.9/spl deg/ rms. This architecture is also suitable for direct frequency modulation, without necessitating any calibration system.

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F. Amorosa

Papers

A DDS-based PLL for 2.4-GHz frequency synthesis