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F

F. Pollara

Researcher at California Institute of Technology

Publications -  9
Citations -  2180

F. Pollara is an academic researcher from California Institute of Technology. The author has contributed to research in topics: Turbo code & Serial concatenated convolutional codes. The author has an hindex of 7, co-authored 9 publications receiving 2162 citations. Previous affiliations of F. Pollara include Jet Propulsion Laboratory.

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Serial concatenation of interleaved codes: performance analysis, design and iterative decoding

TL;DR: In this article, the authors derived upper bounds to the average maximum likelihood bit error probability of serially concatenated block and convolutional codes with interleaver, and derived design guidelines for the outer and inner encoders that maximize the interleavers gain and the asymptotic slope of the error probability curves.
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Iterative turbo decoder analysis based on density evolution

TL;DR: In this paper, the authors track the density of extrinsic information in iterative turbo decoders by actual density evolution, and also approximate it by symmetric Gaussian density functions.
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Soft‐input soft‐output modules for the construction and distributed iterative decoding of code networks

TL;DR: Soft-input soft-output building blocks (modules) are presented to construct and iteratively decode in a distributed fashion code networks, a new concept that includes, and generalizes, various forms of concatenated coding schemes.

The Development of Turbo and LDPC Codes for Deep-Space Applications Error-correcting codes that allow very power-efficient information transmission from spacecraft have been developed along with suitable encoding and decoding hardware.

TL;DR: The development of error-correcting codes has been closely coupled with deep-space exploration since the early days of both. as mentioned in this paper describes the research, design, implementation and standardization work that has taken place at NASA's Jet Propulsion Laboratory (JPL) for both turbo and low-density parity-check (LDPC) codes.
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Bandwidth efficient parallel concatenated coding schemes

TL;DR: The authors propose a solution to the parallel concatenation of trellis codes with multilevel amplitude/phase modulations and a suitable iterative decoding structure that outperforms all codes reported in the past for the same throughput.