An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

FinFETs and Other Multi-Gate Transistors provides a comprehensive description of the physics, technology and circuit applications of multigate field-effect transistors (FETs). It explains the physics and properties of these devices, how they are fabricated and how circuit designers can use them to improve the performances of integrated circuits. The International Technology Roadmap for Semiconductors (ITRS) recognizes the importance of these devices and places them in the "Advanced non-classical CMOS devices" category. Of all the existing multigate devices, the FinFET is the most widely known. FinFETs and Other Multi-Gate Transistors is dedicated to the different facets of multigate FET technology and is written by leading experts in the field.

/pdf/finfets-and-other-multi-gate-transistors-541arp307w.pdf

FinFETs and Other Multi-Gate Transistors

For more than four decades, transistors have been shrinking exponentially in size, and therefore the number of transistors in a single microelectronic chip has been increasing exponentially. Such an increase in packing density was made possible by continually shrinking the metal–oxide–semiconductor field-effect transistor (MOSFET). In the current generation of transistors, the transistor dimensions have shrunk to such an extent that the electrical characteristics of the device can be markedly degraded, making it unlikely that the exponential decrease in transistor size can continue. Recently, however, a new generation of MOSFETs, called multigate transistors, has emerged, and this multigate geometry will allow the continuing enhancement of computer performance into the next decade.

Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors

An improved method is presented for calculating the ionization rates αn and αp from charge multiplication measurements on diffused silicon p-n junctions. The main features of this method are: The real impurity profile is approximated by an exponential function whose parameters are calculated from capacitance measurements; the ratio γ = αp/αn as a function of the electric field is calculated from multiplication measurements; the ionization rates are solved from the ionization integral for pure electron injection, taking the influence of the threshold energy into account. Measurements on narrow junctions agree with measurements on wide junctions by assuming a threshold energy of 1.8 eV for electrons, in agreement with the results of M oll and van O verstraeten .(1) The ionization rates differ from those of M oll and van O verstraeten (1) and of L ee , L ogan et al.(2) mainly because these authors neglect the influence of the threshold energy. The electron and hole data satisfy Chynoweth's law α(E) = α ∞ exp (−b/¦E¦), cm −1 with: for electrons α∞ = 7.03 × 105 cm−1 b = 1.231 × 106 V cm−1 for 1.75 × 105 ⩽ E ⩽ 6.0 × 105 V cm−1 for holes α∞ = 1.582 × 106 cm−1b = 2.036 × 106 V cm−1 for 1.75 × 105 ⩽ E ⩽ 4.0 × 105 V cm−1 and α∞ = 6.71 × 105 cm−1b = 1.693 × 106 V cm−1 for 4.0 × 105 ⩽ E ⩽ 6.0 × 105 V cm−1 Breakdown voltages are computed for high voltage p-n and p-i-n diodes. These are in good agreement with experiments, indicating the reliability of the ionization rates.

Measurement of the ionization rates in diffused silicon p-n junctions

Ever since the first publications by R.J. Schwartz in 1975, research into back-contact cells as an alternative to cells with a front and rear contact has remained a research topic. In the last decade, interest in back-contact cells has been growing and a gradual introduction to industrial applications is emerging. The goal of this review is to present a comprehensive summary of results obtained throughout the years. Back-contact cells are divided into three main classes: back-junction (BJ), emitter wrap-through (EWT) and metallisation wrap-through (MWT), each introduced as logical descendents from conventional solar cells. This deviation from the chronology of the developments is maintained during the discussion of technological results. In addition to progress on manufacturing these cells, aspects of cell modelling and module manufacturing are discussed and an outlook towards industrial implementation is presented. Copyright © 2005 John Wiley & Sons, Ltd.

Back-contact solar cells : A review

An analytical model valid near and below threshold is derived for double-gate nMOS/SOI devices. The model is based on Poisson's equation, containing both the doping impurity charges and the electron concentration. An original assumption of the constant difference between surface and mid-film potentials is successfully introduced. The model provides explicit expressions of the threshold voltage and threshold surface potential, which may no longer be assumed to be pinned at the limit of strong inversion, and demonstrates the nearly ideal subthreshold slope of ultrathin double-gate SOI transistors. Very good agreement with numerical simulations is observed. Throughout the paper we give an insight into weak inversion mechanisms occurring in thin double-gate structures. >

Modeling of ultrathin double-gate nMOS/SOI transistors

The model describes correctly the drain current and the small signal parameters in all regions of operation, including the subthreshold regime and the saturation regime. The model contains as an approximation the charge-sheet model proposed b Brews (see ibid., vol.21, p.345, 1978). Mobility variations along the channel, resulting from the normal and lateral electric fields, can be taken into account.

A long-channel MOSFET model

Accumulation-mode PMOS transistors on SOI (silicon on insulator) are characterized by several conduction mechanisms. Measurements of the threshold voltage corresponding to each of them are presented for the first time. An intuitive physical interpretation of their dependence on the front- and back-gate voltages is also given. >

Measurement of threshold voltages of thin-film accumulation-mode PMOS/SOI transistors

This paper presents accurate device models (1-3 percent) to describe the I_{D}-V_{D} electrical characteristics of surface-channel PMOS transistors in strong inversion, and ion-implanted depletion-mode buried-channel PMOS transistors. The primary emphasis is an accurate description of the transverse carrier mobility with distance and normal electrical field in long-channel structures. The influence of substrate bias on carrier mobility in the surface-channel device is modeled theoretically and verified by experiment. The carrier mobility in the buried-channel devices is constant as determined experimentally with gated-diode C-V and conductance measurements. The modeling parameters are determined at V_{D} = 0 with an automated data-acquisition micro-processor-controlled system. The models are analyzed with a least squares estimation criterion and a high degree of internal consistency is apparent from the statistical significance of the results.

High-accuracy MOS models for computer-aided design

An analytical model for the subthreshold slope of the accumulation-mode p-channeI SOI MOSFET is developed. The exact solution of the equations reveals that the subthreshold swing is slightly larger (by a few percent) than that of enhancement (inversion-mode) fully depleted SOI devices. In most cases, however, the classical subthreshold slope expression developed for inversion-mode fully depleted SOI MOSFET can be used as a good approximation for accumulation-mode devices, which means that the subthreshoId swing tends to the ideal value of S-0 = kT/q 1n(10) mV/dec if the buried oxide is sufficiently thick and if the interface trap density is sufficiently low.

F. Van de Wiele

Papers

Modeling of ultrathin double-gate nMOS/SOI transistors

A long-channel MOSFET model

Measurement of threshold voltages of thin-film accumulation-mode PMOS/SOI transistors

High-accuracy MOS models for computer-aided design

Subthreshold slope of long-channel accumulation-mode p-channel SOI MOSFETs