F
F. Van de Wiele
Researcher at Université catholique de Louvain
Publications - 64
Citations - 923
F. Van de Wiele is an academic researcher from Université catholique de Louvain. The author has contributed to research in topics: Subthreshold conduction & Threshold voltage. The author has an hindex of 15, co-authored 64 publications receiving 900 citations. Previous affiliations of F. Van de Wiele include Catholic University of Leuven.
Papers
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Modeling of ultrathin double-gate nMOS/SOI transistors
TL;DR: In this paper, an analytical model valid near and below threshold is derived for double-gate nMOS/SOI devices, which is based on Poisson's equation, containing both the doping impurity charges and the electron concentration.
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A long-channel MOSFET model
TL;DR: The model described correctly the drain current and the small signal parameters in all regions of operation, including the subthreshold regime and the saturation regime, in this article, where mobility variations along the channel, resulting from the normal and lateral electric fields, can be taken into account.
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Measurement of threshold voltages of thin-film accumulation-mode PMOS/SOI transistors
TL;DR: In this article, the threshold voltage corresponding to each of the conduction mechanisms was measured for the first time and an intuitive physical interpretation of their dependence on the front and back-gate voltages was also given.
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High-accuracy MOS models for computer-aided design
TL;DR: An accurate description of the transverse carrier mobility with distance and normal electrical field in long-channel structures and the influence of substrate bias on carrier mobility in the surface-channel device is modeled theoretically and verified by experiment.
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Subthreshold slope of long-channel accumulation-mode p-channel SOI MOSFETs
TL;DR: An analytical model for the sub-threshold slope of the accumulation-mode p-channeI SOI MOSFET is developed in this article, where the exact solution of the equations reveals that the subthreshold swing is slightly larger (by a few percent) than that of enhancement (inversion-mode) fully depleted SOI devices.