Showing papers by "Fabrizio Lombardi published in 1995"

Diagnosis of interconnects and FPICs using a structured walking-1 approach

Abstract: This paper presents a generalized new approach for testing interconnects (for boundary scan architectures) as well as field programmable interconnect chips (FPICs). The proposed structural test method explicitly avoids aliasing and confounding and as applicable to dense as well as sparse layouts. The proposed method is applicable to both one-step and two-step test generation and diagnosis. Two algorithms with an execution complexity of O(n/sup 2/), where n is the number of nets in the interconnect, are given. Simulation results for benchmark and randomly generated layouts show a substantial reduction in the number of tests using the proposed approaches compared with previous approaches. The applicability of the proposed approach to FPICs is discussed and evaluated by simulation.

Testing of Uncustomized Segmented Channel Field Programmable Gate Arrays

Abstract: This paper presents a methodology for production-time testing of (uncustomized) segmented channel field programmable gate arrays (FPGAs) such as those manufactured by Actel. The principles of this methodology are based on configuring the uncommitted modules (made of sequential and combinational logic circuits) of the FPGA as a set of disjoint one-dimensional arrays similar to iterative logic arrays (ILAs). These arrays can then be tested by establishing appropriate conditions such as constant testability (C-testability). A design approach is proposed. This approach is based on adding a small circuitry (consisting of two transistors) between each pair of uncustomized modules in a row for establishing the ILA configuration as a one-dimensional unilateral array. It also requires the addition of a further primary pin. Features such as number of test vectors and hardware requirements (measured by the number of additional transistors and primary input/output pins) are analyzed; it is shown that the proposed design approach requires a considerably smaller number of test vectors (a reduction of more than two orders of magnitude) and hardware overhead for the testing circuitry (a reduction of 13.6%) than the original FPGA configuration of [Actel Corporation, FPGA Data Book and Design Guide, Sunnyvale]. The proposed approach requires 8+2n_f vectors for testing the uncommitted FPGA of [Actel Corporation, FPGA Data Book and Design Guide, Sunnyvale], where nf is the number of flip-flops (equal to the number of sequential modules for the FPGA of [Actel Corporation, FPGA Data Book and Design Guide, Sunnyvale]) in a row of the FPGA.

A new diagnosis approach for short faults in interconnects

Abstract: Existing one-step diagnosis approaches for faults in interconnects either yield a long test sequence, or use a non-generalized procedure to generate a shorter test sequence We propose a new diagnosis approach for short faults in interconnects The pin-adjacency fault model is assumed By using a divide-and-conquer strategy, our approach can generate a very compact test vector sequence which can diagnose an unrestricted number of short faults Our experiments for three benchmarks as well as large random interconnects (up to 50,000 nets) show that our approach can achieve more than 50% savings in the length of the generated test sequence This can significantly save the diagnosis cost for boundary-scan testing An adaptive diagnosis approach is further proposed to dynamically truncate the originally generated test sequence based on the current information of faulty nets The performance of our adaptive approach in terms of the on-line test generation time and the resulting test sequence length is better than for existing adaptive diagnosis approaches when the fault rate is not very small, such as in a new product line If a low complexity for the ATE is of major importance, then the proposed one-step approach is the best choice >

A row-based FPGA for single and multiple stuck-at fault detection

Abstract: This paper presents a practical and low cost design-for-testability (DFT) scheme for the row-based field programmable gate array (FPGA) which is widely used for rapid prototyping, hardware verification/emulation of VLSI chips and manufacturing of complex digital systems. A new module is introduced for the DFT of the FPGA. The proposed DFT scheme permits the uncommitted FPGA to be tested using a set of constant cardinality (C-testability) for single and multiple stuck-at fault detection, while reducing the number of required primary test pins to only one. The number of tests for the FPGA is still 8+n/sub f/ (where n/sub f/ is the number of sequential modules in a row of the array), but only one primary pin and a small amount of testing circuitry are now required. This paper also modifies the single fault test set to accomplish multiple fault detection under two multiple fault models: the multiple fault single module (MFSM) and the single fault multiple module (SFMM) models. It is shown that by appropriately changing the don't care entries in the vectors of the test set for single fault detection, 100% and nearly 100% fault coverages can be achieved under the MFSM and SFMM models respectively.

Yield analysis of fault-tolerant multichip module systems for massively parallel computing

Abstract: This paper presents analytical models for evaluating the overall yield of systems manufactured using fault-tolerant multichip modules (MCMs) for massively parallel computing. In the proposed approaches, we employ a novel Markov model to compute the yield. Unlike a previous method which utilizes a binomial distribution, our scheme can employ intermediate tests. Several strategies for appropriately testing fault-tolerant MCMs have been proposed, but little analytical evaluation has been performed. In this paper, it is shown that an efficient test strategy with a modest level of redundancy may exist to achieve virtually 100% first-pass MCM yield for a particular system. We note that a yield-analysis model employing the LRT (Least Recently Tested) test strategy proposed in this paper may provide a very good figure of merit due to its cost, delivery, number of tests and reliability benefits for today's technology. Extensive parametric results for the analysis are provided to show that our approach can be applied to calculate the overall yield for fault-tolerant MCMs more accurately and efficiently, thereby improving upon the reliability of the entire system.

An improved approach to fault tolerant rank order filtering on a SIMD mesh processor

Abstract: This paper presents an approach for the fault tolerant computation of the rank order filtering on a SIMD (Single Instruction Multiple Data) mesh processes such as the MasPar. The proposed approach improves over a previous approach in two respects: by changing the data dependency in the execution of the rank order filtering, a new algorithm with constant execution time complexity can be designed; and by introducing a dependency for the rank values of faulty PEs as computed by neighboring (fault free) processing elements (PEs), a lower distortion can be achieved for enhancement of the image.

Modeling intermediate tests for fault-tolerant multichip module systems

Abstract: This paper presents analytical models for evaluating intermediate tests for yield enhancement and quality assurance of systems manufactured using fault-tolerant multichip modules (MCM's) for massively parallel computing (MPC). In the proposed approaches, we employ both a novel Markov model and a so-called working-test-set to compute the yield. Unlike a previous method which utilizes a binomial distribution, our scheme can employ intermediate tests to meet MCM quality requirements effectively. Several strategies for appropriately testing fault-tolerant MCM's have been proposed, but little analytical evaluation has been performed. In this paper, it is shown that an efficient test strategy with a modest level of redundancy may exist to achieve virtually 100% first-pass MCM yield for a particular system. We note that a yield-analysis model employing the LRTWS (Least Recently Tested in WS) test strategy proposed in this paper may provide a very good figure of merit due to its cost, delivery, number of tests and reliability benefits for current technology. Extensive parametric results for the analysis are provided to show that our approach can be applied to calculate the overall yield for fault-tolerant MCM's more accurately and efficiently, thereby improving upon the reliability and quality of the entire system. >

Repair algorithms for mirrored disk systems

Abstract: This paper analyzes different repair methods of a mirrored disk subsystem. The main interest is focused on disk faults and how the repair process is copying data from a fault-free disk to a spare disk with the least performance degradation for user disk requests. The objective of this study is to compare how different repair algorithms affect system performance. Two different repair algorithms are compared. Two different access patterns (uniform and non-uniform) are studied to establish their effects on the repair process and performance. Simulation results of this research indicate that the performance degradation of user disk requests can be significantly reduced by introducing a short delay in the repair algorithm. A new algorithm for detecting sector faults is also presented. This algorithm scans the disk space, while there are no user disk requests issued and detects deteriorated media using the advanced statistics of modern SCSI disks. The advantage of the proposed algorithm is that it can repair the disk subsystem before data is actually lost due to a media defect (bad sector).

Modeling intermediate tests for fault-tolerant multichip module systems

Abstract: This paper presents analytical models for evaluating intermediate tests for yield enhancement and quality assurance of systems manufactured using fault-tolerant multichip modules (MCM's) for massively parallel computing (MPC). In the proposed approaches, we employ both a novel Markov model and a so-called working-test-set to compute the yield. Unlike a previous method [1] which utilizes a binomial distribution, our scheme can employ intermediate tests to meet MCM quality requirements effectively. Several strategies for appropriately testing fault-tolerant MCM's have been proposed, but little analytical evaluation has been performed. In this paper, it is shown that an efficient test strategy with a modest level of redundancy may exist to achieve virtually 100% first-pass MCM yield for a particular system. We note that a yield-analysis model employing the LRTWS (Least Recently Tested in WS) test strategy proposed in this paper may provide a very good figure of merit due to its cost, delivery, number of tests and reliability benefits for current technology. Extensive parametric results for the analysis are provided to show that our approach can be applied to calculate the overall yield for fault-tolerant MCM's more accurately and efficiently, thereby improving upon the reliability and quality of the entire system.

Accurate communication models for task scheduling in multicomputers

Abstract: Models for computations and message-passing communications are very important for scheduling applications onto multicomputer systems and estimating the parallel execution time. This paper presents new models for communication, scheduling and estimating the execution time. In the proposed models, it is assumed that each processor in the multicomputer system has a router. The processor can only receive data from and send data to the router sequentially while the router can receive data from and send data to the routers of other processors in parallel. The execution time of a given application on a given machine can be then accurately estimated by using the proposed models. The input parameters to the proposed models are determined by measuring some parameters experimentally. Experimental results on the nCUBE2 machine are given to show the correctness of the proposed models.

Fault-tolerant sorting in SIMD hypercubes

Abstract: This paper considers sorting in SIMD hypercube multiprocessors in the presence of node failures. The proposed algorithm correctly sorts up to 2/sup n/=N keys in a faulty SIMD hypercube of dimension n containing up to n-1 faulty nodes. The proposed fault-tolerant algorithm employs radix sort. We use a pair of flood dimensions which helps to route data around the faulty processors during the movement of data. If all the key values to be sorted belong to the range 0 to M-1, sorting can be accomplished efficiently in O(log M*log N)+O(log/sup 2/N) time. >

Optimal switching networks for WSI architectures with fault tolerant path routing

Abstract: This paper presents an approach for designing fault-tolerant routers for signal distribution by redundant path routing in wafer scale integration (WSI) architectures. The conditions by which a router can be designed using spare lines (tracks) such that the probability of successfully routing all input lines in the prescribed order and in the presence of faults in switches can be optimized (optimality), are proved using a probabilistic analysis. An algorithm which determines the placement of the switches in the router to satisfy the optimality conditions is presented.