An experimental technique is described for observing the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate Various approaches to reducing substrate crosstalk (the use of physical separation of analog and digital circuits, guard rings, and a low-inductance substrate bias) are evaluated experimentally for a CMOS technology with a substrate comprising an epitaxial layer grown on a heavily doped bulk wafer Observations indicate that reducing the inductance in the substrate bias is the most effective Device simulations are used to show how crosstalk propagates via the heavily doped bulk and to predict the nature of substrate crosstalk in CMOS technologies integrated in uniform, lightly doped bulk substrates, showing that in such cases the substrate noise is highly dependent on layout geometry A method of including substrate effects in SPICE simulations for circuits fabricated on epitaxial, heavily doped substrates is developed >

Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits

Remote laboratories have been introduced during the last few decades into engineering education processes as well as integrated within e-learning frameworks offered to engineering and science students. Remote laboratories are also being used to support life-long learning and student's autonomous learning activities. In this paper, after a brief overview of state-of-the-art technologies in the development of remote laboratories and presentation of recent and interesting examples of remote laboratories in several areas related with industrial electronics education, some current trends and challenges are also identified and discussed.

Current Trends in Remote Laboratories

Neuromorphic systems are gaining increasing importance in an era where CMOS digital computing techniques are meeting hard physical limits. These silicon systems mimic extremely energy efficient neural computing structures, potentially both for solving engineering applications as well as understanding neural computation. Towards this end, the authors provide a glimpse at what the technology evolution roadmap looks like for these systems so that Neuromorphic engineers may gain the same benefit of anticipation and foresight that IC designers gained from Moore's law many years ago. Scaling of energy efficiency, performance, and size will be discussed as well as how the implementation and application space of Neuromorphic systems are expected to evolve over time.

/pdf/finding-a-roadmap-to-achieve-large-neuromorphic-hardware-4vszjr2j41.pdf

Finding a roadmap to achieve large neuromorphic hardware systems.

A field-programmable analog array (FPAA) with 32 computational analog blocks (CABs) and occupying 3 × 3 mm2 in 0.35-μm CMOS is presented. Each CAB has a wide variety of subcircuits ranging in granularity from multipliers and programmable offset wide-linear-range Gm blocks to nMOS and pMOS transistors. The programmable interconnects and circuit elements in the CAB are implemented using floating-gate (FG) transistors, the total number of which exceeds fifty thousand. Using FG devices eliminates the need for SRAM to store configuration bits since the switch stores its own configuration. This system exhibits significant performance enhancements over its predecessor in terms of achievable dynamic range (> 9 b of FG voltage) and speed (≈ 20 gates/s) of accurate FG current programming and isolation between ON and OFF switches. An improved routing fabric has been designed that includes nearest neighbor connections to minimize the penalty on bandwidth due to routing parasitic. A maximum bandwidth of 57 MHz through the switch matrix and around 5 MHz for a first-order low-pass filter is achievable on this chip, the limitation being a “program” mode switch that will be rectified in the next chip. Programming performance improved drastically by implementing the entire algorithm on-chip with an SPI digital interface. Measured results of the individual subcircuits and two system examples including an AM receiver and a speech processor are presented.

A Floating-Gate-Based Field-Programmable Analog Array

Field-programmable analog arrays (FPAAs) provide a method for rapidly prototyping analog systems. Currently available commercial and academic FPAAs are typically based on operational amplifiers (or other similar analog primitives) with only a few computational elements per chip. While their specific architectures vary, their small sizes and often restrictive interconnect designs leave current FPAAs limited in functionality and flexibility. For FPAAs to enter the realm of large-scale reconfigurable devices such as modern field-programmable gate arrays (FPGAs), new technologies must be explored to provide area-efficient accurately programmable analog circuitry that can be easily integrated into a larger digital/mixed-signal system. Recent advances in the area of floating-gate transistors have led to a core technology that exhibits many of these qualities, and current research promises a digitally controllable analog technology that can be directly mated to commercial FPGAs. By leveraging these advances, a new generation of FPAAs is introduced in this paper that will dramatically advance the current state of the art in terms of size, functionality, and flexibility. FPAAs have been fabricated using floating-gate transistors as the sole programmable element, and the results of characterization and system-level experiments on the most recent FPAA are shown.

https://knowledge.e.southern.edu/cgi/viewcontent.cgi?article=1005&context=facworks_comp

Large-scale field-programmable analog arrays for analog signal processing

An analog circuit synthesis tool based on efficient and reliable yield estimation

Design, implementation, and evaluation of a backstepping control algorithm for an active ankle–foot orthosis

In this paper we present an analog 5th order GM-S low-pass filter structure using ten identical operational transconductance amplifiers (OTA) for high speed wireless systems. A linear OTA that can be tuned by a single bias current, which is provided by a 5-bit current DAC, was designed. The 3dB cut-off frequency of the filter can be tuned from 6 MHz to 40 MHz. IM3 of the 40 MHz 5th order low-pass filter is −60 dB with 400 mV p-p input voltage, 1.2 V supply voltage, and approximately 8.4 mW power consumption. Layout of the proposed filter occupies 0.07 mm2 IC area in 90nm single-poly 9 metal layer CMOS technology. Post-layout simulation waveforms are obtained using Eldo simulation environment of MentorGraphics tool suit.

Design of a digitally tunable 5 th order GM-C filter using linearized OTA in 90nm CMOS technology

With the continuous downscaling of CMOS technology over the last two decades, reliability of CMOS circuits has become a more critical design issue due to the worsening effects of process variations. Conventionally, variability analysis has been performed following the design process after which the design is modified based on the variation effects, if necessary. However, increased variation and mismatch problems have enforced designers to consider robustness as a design objective that should be maximized. Besides the variability problem, increased non-idealities with more advanced technologies have complicated circuit analysis, and caused unacceptably long design times. Therefore, design automation tools for analog circuits have become crucial to keep the synthesis time within acceptable limits even if variability analysis is included. In this paper, two different methodologies are proposed and discussed for variation aware design automation of analog circuits: Over-Design approach that is based on guard-banding the circuit performance and Variation-Aware Design approach depending on looking for more robust solutions in the dedicated search space. The superiorities of the proposed approaches are discussed via the synthesis results of a two stage OTA example.

http://ieeexplore.ieee.org/iel7/6863139/6872647/06872737.pdf

Sensitivity based methodologies for process variation aware analog IC optimization

Modelling of the degradation mechanisms has a crucial role during the aging analysis, which determines the accuracy of the lifetime estimation. Conventionally, analytical and semi-empirical models are utilized during the aging analysis. Analytical models employ deterministic equations during the degradation calculation and they can be scaled for different technology nodes; hence providing flexibility. However, scaling errors and approximations during the model development may degrade the accuracy. On the other hand, semi-empirical models are generated via accelerated aging test (AAT) performed on the silicon, which often promise more reliable results for a given technology. This paper comprehensively examines the semi-empirical modelling process from test chip design to AAT experiments.

Faik Baskaya

Papers

An analog circuit synthesis tool based on efficient and reliable yield estimation

Design, implementation, and evaluation of a backstepping control algorithm for an active ankle–foot orthosis

Design of a digitally tunable 5 th order GM-C filter using linearized OTA in 90nm CMOS technology

Sensitivity based methodologies for process variation aware analog IC optimization

Semi-empirical aging model development via accelerated aging test