An experimental technique is described for observing the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate Various approaches to reducing substrate crosstalk (the use of physical separation of analog and digital circuits, guard rings, and a low-inductance substrate bias) are evaluated experimentally for a CMOS technology with a substrate comprising an epitaxial layer grown on a heavily doped bulk wafer Observations indicate that reducing the inductance in the substrate bias is the most effective Device simulations are used to show how crosstalk propagates via the heavily doped bulk and to predict the nature of substrate crosstalk in CMOS technologies integrated in uniform, lightly doped bulk substrates, showing that in such cases the substrate noise is highly dependent on layout geometry A method of including substrate effects in SPICE simulations for circuits fabricated on epitaxial, heavily doped substrates is developed >

Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits

Remote laboratories have been introduced during the last few decades into engineering education processes as well as integrated within e-learning frameworks offered to engineering and science students. Remote laboratories are also being used to support life-long learning and student's autonomous learning activities. In this paper, after a brief overview of state-of-the-art technologies in the development of remote laboratories and presentation of recent and interesting examples of remote laboratories in several areas related with industrial electronics education, some current trends and challenges are also identified and discussed.

Current Trends in Remote Laboratories

Neuromorphic systems are gaining increasing importance in an era where CMOS digital computing techniques are meeting hard physical limits. These silicon systems mimic extremely energy efficient neural computing structures, potentially both for solving engineering applications as well as understanding neural computation. Towards this end, the authors provide a glimpse at what the technology evolution roadmap looks like for these systems so that Neuromorphic engineers may gain the same benefit of anticipation and foresight that IC designers gained from Moore's law many years ago. Scaling of energy efficiency, performance, and size will be discussed as well as how the implementation and application space of Neuromorphic systems are expected to evolve over time.

/pdf/finding-a-roadmap-to-achieve-large-neuromorphic-hardware-4vszjr2j41.pdf

Finding a roadmap to achieve large neuromorphic hardware systems.

A field-programmable analog array (FPAA) with 32 computational analog blocks (CABs) and occupying 3 × 3 mm2 in 0.35-μm CMOS is presented. Each CAB has a wide variety of subcircuits ranging in granularity from multipliers and programmable offset wide-linear-range Gm blocks to nMOS and pMOS transistors. The programmable interconnects and circuit elements in the CAB are implemented using floating-gate (FG) transistors, the total number of which exceeds fifty thousand. Using FG devices eliminates the need for SRAM to store configuration bits since the switch stores its own configuration. This system exhibits significant performance enhancements over its predecessor in terms of achievable dynamic range (> 9 b of FG voltage) and speed (≈ 20 gates/s) of accurate FG current programming and isolation between ON and OFF switches. An improved routing fabric has been designed that includes nearest neighbor connections to minimize the penalty on bandwidth due to routing parasitic. A maximum bandwidth of 57 MHz through the switch matrix and around 5 MHz for a first-order low-pass filter is achievable on this chip, the limitation being a “program” mode switch that will be rectified in the next chip. Programming performance improved drastically by implementing the entire algorithm on-chip with an SPI digital interface. Measured results of the individual subcircuits and two system examples including an AM receiver and a speech processor are presented.

A Floating-Gate-Based Field-Programmable Analog Array

Field-programmable analog arrays (FPAAs) provide a method for rapidly prototyping analog systems. Currently available commercial and academic FPAAs are typically based on operational amplifiers (or other similar analog primitives) with only a few computational elements per chip. While their specific architectures vary, their small sizes and often restrictive interconnect designs leave current FPAAs limited in functionality and flexibility. For FPAAs to enter the realm of large-scale reconfigurable devices such as modern field-programmable gate arrays (FPGAs), new technologies must be explored to provide area-efficient accurately programmable analog circuitry that can be easily integrated into a larger digital/mixed-signal system. Recent advances in the area of floating-gate transistors have led to a core technology that exhibits many of these qualities, and current research promises a digitally controllable analog technology that can be directly mated to commercial FPGAs. By leveraging these advances, a new generation of FPAAs is introduced in this paper that will dramatically advance the current state of the art in terms of size, functionality, and flexibility. FPAAs have been fabricated using floating-gate transistors as the sole programmable element, and the results of characterization and system-level experiments on the most recent FPAA are shown.

https://knowledge.e.southern.edu/cgi/viewcontent.cgi?article=1005&context=facworks_comp

Large-scale field-programmable analog arrays for analog signal processing

With the growing use of analog circuits in sensor systems for internet of things applications, estimation of their yield has become critical in order to increase the efficiency of large volume manufacturing. In this paper, a methodology to estimate the yield of analog circuits beyond 95% is proposed. The methodology is based on an algorithm that uses adaptive sampling to approach the “tail” region of the initial distribution which contains the dysfunctional units. These units do not satisfy the initial design targets thereby lowering the yield. An inverter and a two-stage operational amplifier have been used to verify the methodology where the reference distribution is based on 10^6 samples for both circuits. Simulation results reveal that the accuracy for 95%, 98%, and 99% yield has been compromised by less than 2.1%, 5.7%, and 7.4%, respectively, whereas the computation cost is reduced by 20x.

A Rare Event Based Yield Estimation Methodology for Analog Circuits

Modern advances in reconfigurable analog technologies are allowing field-programmable analog arrays (FPAAs) to dramatically grow in size, flexibility, and usefulness. With these advances, analog circuits and systems can be programmable, reconfigurable, adaptive, implemented on standard CMOS to take advantage of scaled CMOS technology, and at a density comparable to digital memories. Our goal in this paper is to develop the first physical design automation toolset for floating-gate based FPAA with focus on minimization of parasitic effects on FPAA interconnect. We provide graph-based analog circuit and FPAA device modeling suitable for efficient mapping. Our FPAA clustering algorithm constructs Computational Analog Blocks (CAB) from analog circuit elements while improving the utilization of the device and reducing its impact on the total number of routing switches used. Experimental results demonstrate the effectiveness of our approach.

http://www.gtcad.gatech.edu/www/papers/ispd05.pdf

Mapping algorithm for large-scale field programmable analog array

Analog circuits and systems research and education can significantly benefit from the computational flexibility provided by large-scale FPAAs. The component density of these devices is sufficient to synthesize large systems in a short period of time. However, this level of reconfigurable and programmable complexity requires a development platform and CAD tools to demonstrate the capabilities of large-scale FPAAs before they can be widely accepted. To address this need, a self-contained FPAA setup has been developed along with an integrated software design flow. With only an Ethernet connection and an AC power outlet, a researcher or student can explore the numerous analog circuit possibilities provided by large-scale FPAAs.

Faik Baskaya

Papers

A Rare Event Based Yield Estimation Methodology for Analog Circuits

Mapping algorithm for large-scale field programmable analog array

A Self-Contained Large-Scale FPAA Development Platform

Layout tools for analog integrated circuits and mixed-signal systems-on-chip: A survey

Layout Tools for Analog Integrated Circuits and Mixed-Signal Systems-on-Chip