An experimental technique is described for observing the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate Various approaches to reducing substrate crosstalk (the use of physical separation of analog and digital circuits, guard rings, and a low-inductance substrate bias) are evaluated experimentally for a CMOS technology with a substrate comprising an epitaxial layer grown on a heavily doped bulk wafer Observations indicate that reducing the inductance in the substrate bias is the most effective Device simulations are used to show how crosstalk propagates via the heavily doped bulk and to predict the nature of substrate crosstalk in CMOS technologies integrated in uniform, lightly doped bulk substrates, showing that in such cases the substrate noise is highly dependent on layout geometry A method of including substrate effects in SPICE simulations for circuits fabricated on epitaxial, heavily doped substrates is developed >

Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits

Remote laboratories have been introduced during the last few decades into engineering education processes as well as integrated within e-learning frameworks offered to engineering and science students. Remote laboratories are also being used to support life-long learning and student's autonomous learning activities. In this paper, after a brief overview of state-of-the-art technologies in the development of remote laboratories and presentation of recent and interesting examples of remote laboratories in several areas related with industrial electronics education, some current trends and challenges are also identified and discussed.

Current Trends in Remote Laboratories

Neuromorphic systems are gaining increasing importance in an era where CMOS digital computing techniques are meeting hard physical limits. These silicon systems mimic extremely energy efficient neural computing structures, potentially both for solving engineering applications as well as understanding neural computation. Towards this end, the authors provide a glimpse at what the technology evolution roadmap looks like for these systems so that Neuromorphic engineers may gain the same benefit of anticipation and foresight that IC designers gained from Moore's law many years ago. Scaling of energy efficiency, performance, and size will be discussed as well as how the implementation and application space of Neuromorphic systems are expected to evolve over time.

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Finding a roadmap to achieve large neuromorphic hardware systems.

A field-programmable analog array (FPAA) with 32 computational analog blocks (CABs) and occupying 3 × 3 mm2 in 0.35-μm CMOS is presented. Each CAB has a wide variety of subcircuits ranging in granularity from multipliers and programmable offset wide-linear-range Gm blocks to nMOS and pMOS transistors. The programmable interconnects and circuit elements in the CAB are implemented using floating-gate (FG) transistors, the total number of which exceeds fifty thousand. Using FG devices eliminates the need for SRAM to store configuration bits since the switch stores its own configuration. This system exhibits significant performance enhancements over its predecessor in terms of achievable dynamic range (> 9 b of FG voltage) and speed (≈ 20 gates/s) of accurate FG current programming and isolation between ON and OFF switches. An improved routing fabric has been designed that includes nearest neighbor connections to minimize the penalty on bandwidth due to routing parasitic. A maximum bandwidth of 57 MHz through the switch matrix and around 5 MHz for a first-order low-pass filter is achievable on this chip, the limitation being a “program” mode switch that will be rectified in the next chip. Programming performance improved drastically by implementing the entire algorithm on-chip with an SPI digital interface. Measured results of the individual subcircuits and two system examples including an AM receiver and a speech processor are presented.

A Floating-Gate-Based Field-Programmable Analog Array

Field-programmable analog arrays (FPAAs) provide a method for rapidly prototyping analog systems. Currently available commercial and academic FPAAs are typically based on operational amplifiers (or other similar analog primitives) with only a few computational elements per chip. While their specific architectures vary, their small sizes and often restrictive interconnect designs leave current FPAAs limited in functionality and flexibility. For FPAAs to enter the realm of large-scale reconfigurable devices such as modern field-programmable gate arrays (FPGAs), new technologies must be explored to provide area-efficient accurately programmable analog circuitry that can be easily integrated into a larger digital/mixed-signal system. Recent advances in the area of floating-gate transistors have led to a core technology that exhibits many of these qualities, and current research promises a digitally controllable analog technology that can be directly mated to commercial FPGAs. By leveraging these advances, a new generation of FPAAs is introduced in this paper that will dramatically advance the current state of the art in terms of size, functionality, and flexibility. FPAAs have been fabricated using floating-gate transistors as the sole programmable element, and the results of characterization and system-level experiments on the most recent FPAA are shown.

https://knowledge.e.southern.edu/cgi/viewcontent.cgi?article=1005&context=facworks_comp

Large-scale field-programmable analog arrays for analog signal processing

Assertion-based methodology is gaining popularity in analog and mixed-signal (AMS) verification. Early AMS assertion languages are built on digital assertion languages. This results in limited native support to express most low-level aspects of AMS properties. We present three analog layer extensions to increase analog expressiveness in AMS assertion languages. We first describe the concept of haloes, an implicit way to handle tolerance values of analog signals in assertions. Then, booleanization of analog signals using dual-threshold is introduced to solve problems caused by fluctuations on signals. Finally, we integrate analog measurement operators into assertions. We validate our extensions using our prototype tool on a 10-bit two-stage pipelined analog-to-digital converter design.

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Analog layer extensions for analog/mixed-signal assertion languages

This work presents a synthesis framework that generates a formally verifiable RTL from a high level language. We develop an estimation model for area, delay and power metrics of arithmetic components for Xilinx Spartan 3 FPGA family. Our estimation model works 300 times faster than Xilinx's toolchain with an average error of 6.57\% for delay and 3.76\% for area estimations. Our framework extracts CDFGs from ANSI-C, LRH(+) \cite{Kurumahmut2009} and VHDL. CDFGs are verified using the symbolic model checker NuSMV \cite{nusmv} with temporal logic properties. This method guarantees detection of hardware redundancy and word-length mismatch related bugs by static code checking.

/pdf/a-verifiable-high-level-data-path-synthesis-framework-4pyjqomzmi.pdf

A Verifiable High Level Data Path Synthesis Framework

In this paper, a Field Programmable Analog Array design for biomedical applications is presented. It is known that general purpose FPAA’s have low performance in very low frequency applications because of analog design limitations. In this paper, FPAA design using AMS 0.35 µm technology for very low frequency and low power is presented.

Biyomedikal Uygulamalar için Alan Programlanabilir Analog Dizi Tasarimi (Field Programmable Analog Array Design for Biomedical Applications)

In this paper, a Field Programmable Analog Array design for biomedical applications is presented. It is known that general purpose FPAA's have low performance in very low frequency applications because of analog design limitations. In this paper, FPAA design using AMS 0.35 µm technology for very low frequency and low power is presented.

Field Programmable Analog Array Design for biomedical applications

Performance of analog circuits degrades over time due to several time-dependent degradation mechanisms. Due to the increased aging problems in ever-shrinking dimensions, reliability of complementary metal-oxide-semiconductor analog circuits has become a major concern. Overdesign is a popular aging-aware circuit design approach, where circuit operation is guardbanded by choosing the design point beyond the optimal region. For the sake of reliability, power consumption and chip area are sacrificed in this approach, which is undesirable considering strict energy limitations in modern applications. Conversely, Sense and React (S8R) approach serves the same purpose without any additional power consumption, in which degradation of circuit features is detected by online monitoring and recovered immediately. Furthermore, such systems enable remote control and healing of circuits. However, design of an S8R system is quite complicated. In particular, determination of efficient aging signatures and design of recovery strategy are highly challenging problems. This study thoroughly discusses the design process of S8R systems and proposes computer-aided-design-based design strategies that reduce the designer effort considerably. A novel design automation tool for S8R systems was developed, in which signature selection and recovery determination were integrated. To demonstrate proposed design strategies, two different S8R systems are implemented, simulated, and discussed in detail.

Faik Baskaya

Papers

Analog layer extensions for analog/mixed-signal assertion languages

A Verifiable High Level Data Path Synthesis Framework

Biyomedikal Uygulamalar için Alan Programlanabilir Analog Dizi Tasarimi (Field Programmable Analog Array Design for Biomedical Applications)

Field Programmable Analog Array Design for biomedical applications

On Chip Reconfigurable CMOS Analog Circuit Design and Automation Against Aging Phenomena: Sense and React