F
Federico Mari
Researcher at Sapienza University of Rome
Publications - 53
Citations - 785
Federico Mari is an academic researcher from Sapienza University of Rome. The author has contributed to research in topics: Hybrid system & Model checking. The author has an hindex of 16, co-authored 53 publications receiving 688 citations. Previous affiliations of Federico Mari include Intel.
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Book ChapterDOI
System Level Formal Verification via Model Checking Driven Simulation
TL;DR: It is shown how by combining Explicit Model Checking techniques and simulation it is possible to effectively carry out (bounded) System Level Formal Verification of large Hybrid Systems such as those defined using model-based tools like Simulink.
Proceedings ArticleDOI
System Level Formal Verification via Distributed Multi-core Hardware in the Loop Simulation
TL;DR: The experimental results on the Fuel Control System example in the Simulink distribution show that by using 64 machines with an 8 core processor each the authors can complete the SLFV activity in about 27 hours whereas a sequential approach would require more than 200 days.
Journal ArticleDOI
SyLVaaS: System Level Formal Verification as a Service*
TL;DR: SyLVaaS, a Web-based tool enabling Verification as a Service (VaaS), implements an assume-guarantee approach to the verification problem outlined above and is evaluated by evaluating the system on industry-scale input related to the verify of the Fuel Control System model in the Simulink distribution.
Book ChapterDOI
Computing biological model parameters by parallel statistical model checking
TL;DR: This paper proposes a parallel algorithm designed as to be effectively executed on an arbitrary large cluster of multi-core heterogenous machines to find biologically meaningful parameter values.
Proceedings ArticleDOI
Anytime System Level Verification via Random Exhaustive Hardware in the Loop Simulation
TL;DR: A parallel random exhaustive Hardware In the Loop Simulation based model checker for hybrid systems that is able to provide an upper bound to the probability that the System Under Verification exhibits an error in a yet-to-be-simulated scenario (Omission Probability).