This paper proposes the design and control of a three-phase four-wire distribution static compensator (DSTATCOM) for elimination of several power quality (PQ) issues, namely harmonics, reactive power, load unbalancing, and neutral current. A three-phase voltage source converter (VSC) and a zigzag transformer based configuration are utilized as a DSTATCOM. The zigzag transformer is operated to provide a suitable path for load neutral current and other PQ problems are mitigated by designing a suitable control for VSC. The control of VSC is developed using Euclidean direction search (EDS) technique based adaptive control theory. This control algorithm is designed to extricate fundamental constituents from the load current and used to generate switching pulses for VSC. The improved behavior of the proposed EDS-based control is observed by comparing it with other existing controllers. Real-time performance of the EDS control is verified on a developed prototype in the laboratory using VSC and DSP (dSPACE1104 R&D controller).

Power Quality Enhancement Using Euclidean Direction Search Based Control Technique

Finite-control-set model-based predictive current control (FCS-MPCC) technique is distinguished by a variable switching frequency which causes high harmonic distortion a low sampling frequency. This latter could be considered an undesired behavior for active power filter for grid-connected applications. To overcome this issue, this paper proposes a modulated FCS-MPCC applied to a three-phase four-wire active power filter based on H-bridge converter. Simulation results are developed to demonstrate the efficiency of the proposed modulated FCS-MPCC comparing with classic FCS-MPCC, thus concluding the advantages and limitations of each technique at transient and steady states.

Modulated Predictive Current Control Technique for a Three-Phase Four-Wire Active Power Filter based on H-bridge Two-Level Converter

Unbalanced loads cause the imbalance of the grid current and the resulting imbalance of the grid voltage when the imbalance rate of the grid current increases considerably. To cope with this problem flexibly at low cost, we modify the circuit structure from previously installed $\Delta $ -Y transformer 3-phase 3-leg inverter to split dc-link capacitor 3-leg inverter eliminating the transformer. And then we propose two kinds of compensation algorithms for balancing the grid current that can basically utilize a preinstalled control board. It is divided into reactive compensation, where dc-link of the inverter does not supply effective power to the grid but compensates for the imbalance of grid current, and effective compensation, where dc-link of the inverter supplies effective power to the grid for compensating the unbalanced grid current. We design an additional power calculator board to obtain power information, and apply it to a 10kW prototype, and then verify its validity through PSIM simulation and experiments.

/pdf/imbalance-compensation-of-the-grid-current-using-effective-58rlgb5ful.pdf

Imbalance Compensation of the Grid Current Using Effective and Reactive Power for Split DC-Link Capacitor 3-Leg Inverter

This article presents a triangular coordinate system , a three-dimensional (3-D) coordinate system in which the three axes are oriented at 60° to each other. The 3-D representation of multilevel inverter voltage space vectors and generation of 3-D space vector pulsewidth modulation (3DSVPWM) using this coordinate system is proposed. The proposed 3DSVPWM method offers advantage of simplicity, amenable for implementation in field programmable gate arrays (FPGA) and application specific integrated circuits (ASICs), and flexibility for common-mode voltage control. The existing methods for 3DSVPWM generation operate on a 3-D space, with the axes oriented at 90°. The conventional 3DSVPWM methods require switching among four vectors, located at vertices of a tetrahedron, in a PWM cycle. In addition, the triangular coordinate system offers flexibility to directly extend any two-dimensional SVPWM (2DSVPWM) algorithm to 3-D, since it also involves switching of three vectors located at vertices of a triangle. The proposed method of 3DSVPWM generation is generalized and can be extended to any n-level inverter. The three vectors switched to approximate the reference vector and their corresponding durations are directly determined utilizing arithmetic operations. The coordinate system and the generation of SVPWM utilizing the triangular coordinate system is explained and experimentally validated on a dSPACE DS1104 platform for a five-level open-end winding inverter configuration and results are presented.

A Triangular 3-D Coordinate System for Multilevel SVPWM Generation

Three-phase four-leg four-wire (3P4L4W) three -level (3L) inverters have the ability to supply both balanced and unbalanced loads. This letter establishes common-mode (CM) and differential-mode (DM) circuit models for the 3P4L4W 3L inverter. It is revealed that the 3L phase-leg CM voltage is determined by the voltage balancing control (VBC) for the split dc bus voltages, that the DM load voltages are subject to the DM voltage control for the 3L phase leg, and that the CM load voltage is subject to the control for the fourth phase leg. On this basis, a decoupled modulation is proposed where the 3L phase legs are modulated to attain VBC and closed-loop DM load-voltage control, whereas the fourth phase leg is independently modulated to realize the closed-loop CM load-voltage control. The proposed work has been experimentally verified, showing that the 3P4L4W 3L inverter with this decoupled modulation scheme can provide well-balanced ac load voltages and low total harmonic distortion for any type of ac loads: balanced, unbalanced, linear, and nonlinear. 

Decoupled Modulation With Common-Mode Load-Voltage Control for Three-Phase Four-Leg Three-Level Inverter

Presently, the neutral-point potential offset is an inherent problem for three-level converters on three-phase four-wire active power filters. The conventional three-dimensional space vector pulse width modulation (3-D-SVPWM) strategy is adopted as a normal solution to the problem, but the selection of space vector sectors for four-wire converter is both abstract and complicated in practice. This paper proposes a new PWM strategy accordingly to simplify the selection process and the calculation of duration. Compared to the conventional 3D-SVPWM, the proposed method locates the sector of optimal vector directly with the polarity of three-phase reference voltage. Then, by applying voltage–second balance rule, it can perform a fast calculation of the duration and generate PWM signals to control the switching devices’ on/off. As an approach to correct the imbalance dc-link capacitor voltage, this strategy reconstructs the switching sequence. A portion of state O duration is disassembled into states P and N to suppress the neutral-point potential offset. The proposed strategy is validated with a range of experiments. The results indicate that this simplified PWM strategy can effectively reduce the computational burden, and also the dc-link capacitor voltage is well controlled.

A Simplified PWM Strategy for Three-Level Converters on Three-Phase Four-Wire Active Power Filter

The overheating stress of power devices is the main cause of converter system failures, so real-time temperature acquisition, as well as timely over-temperature protection, under various operating conditions are key to achieving a more reliable energy conversion. In this paper, an improved three-dimensional (3-D) coupled thermal model for insulated gate bipolar transistors (IGBTs) and related heatsink is constructed by considering the thermal coupling effects at both the device- and the module level. Furthermore, the coupled thermal impedance parameters are thereby extracted based on the finite-element method (FEM), so that the dynamic loss and transient temperature distribution under actual working conditions can be obtained based on this electro-thermal coupling model. Meanwhile, to avoid the overheating damage of power devices due to untimely action of the negative temperature coefficient (NTC) thermistor over-temperature protection, this article aims at the idle IGBT device in the three-level neutral-point clamped (NPC) application using IGBT half-bridge modules, combined with the emitter terminal temperature, and finally realizes the multiple over-temperature protection settings. The improved temperature monitoring methods proposed in this paper are realized by the drive and control circuits and verified through simulation and experimental results.

Improved Temperature Monitoring and Protection Method of Three-level NPC Application Based on Half-bridge IGBT Modules

As a control algorithm for high performance of active power filter (APF) systems, finite control set model predictive current control (FCS-MPC) has the disadvantages of unfixed switching frequency and large amount of calculations for three-level APF systems. Therefore, in order to overcome the drawback of FCS-MPC, a simplified Pulse Width Modulation (PWM) strategy based on MPC is proposed in this paper. First, the strategy, with no rolling of all the 27 vectors, adopts the idea of a cost function to obtain the optimal reference vector of each phase. Second, the duration time of each vector in this strategy can be directly calculated by judging the sector of the virtual reference vector. Third, the neutral-point balancing problem is solved by modifying the duration time. In the meantime, the strategy is studied in detail and verified experimentally in this paper. The experiment results indicate the validity and effectiveness of the proposed strategy.

A simplified PWM strategy based on MPC for NPC three-level APF systems

Aiming at the short-circuit (SC) capability for silicon carbide (SiC) MOSFETs due to the limitation of the gate oxide process, that is, the ability of MOSFET to withstand large current and high voltage when the channel is turned on, this paper summarizes and analyses various SC fault types for SiC MOSFETs, which are further simulated through a designed SC test platform with strict timing of control signals. Aiming at the well-explored Hard Switching Fault (HSF) and Fault Under Loading (FUL), the connection between these two and other SC faults is derived, which brings about the proposed improved SC fault adaptive detection and protection in the driving scheme. Because the shorter SC withstand time of SiC MOSFETs puts forward a higher requirement for the response speed, which contradicts the risk of false-triggering, namely, the poor noise immunity caused by merely reducing blanking time. Therefore, the improved SC detection scheme combining drain-source and gate voltage signals proposed in this article enhances the self-adaptation to different SC fault types of SiC MOSFETs through variable blanking time setting, thereby effectively accelerating the detection speed as well as suppressing the SC current, on the premise of ensuring reliable, compatible SC protection. 

Short-Circuit Fault Adaptive Analysis and Protection for SiC MOSFETs

The importance of short-circuit protection in the driving scheme is self-evident, and the key is the realization of fast and accurate short-circuit fault detection. The traditional drain-source voltage $(V_{\text{ds}})$ short-circuit detection method sacrifices the speed to ensure the reliability of short-circuit protection by setting a relatively large blanking time constant. However, the shorter short-circuit withstand time of SiC MOSFET puts forward a higher requirement of short-circuit protection. Therefore, the improved $V_{\text{ds}}$ short-circuit detection method proposed in this article enhances the self-adaptation to different short-circuit faults of SiC MOSFET, as a result speeding up the protection speed.

Fengyou He

Papers

A Simplified PWM Strategy for Three-Level Converters on Three-Phase Four-Wire Active Power Filter

Improved Temperature Monitoring and Protection Method of Three-level NPC Application Based on Half-bridge IGBT Modules

A simplified PWM strategy based on MPC for NPC three-level APF systems

Short-Circuit Fault Adaptive Analysis and Protection for SiC MOSFETs

Improved Drain-source Voltage Detection Method for Short-circuit Protection of SiC MOSFET