Mutation Testing is a fault-based software testing technique that has been widely studied for over three decades The literature on Mutation Testing has contributed a set of approaches, tools, developments, and empirical results This paper provides a comprehensive analysis and survey of Mutation Testing The paper also presents the results of several development trend analyses These analyses provide evidence that Mutation Testing techniques and tools are reaching a state of maturity and applicability, while the topic of Mutation Testing itself is the subject of increasing interest

An Analysis and Survey of the Development of Mutation Testing

The Object Management Group's (OMG) Model Driven Architecture (MDA) strategy envisages a world where models play a more direct role in software production, being amenable to manipulation and transformation by machine. Model Driven Engineering (MDE) is wider in scope than MDA. MDE combines process and analysis with architecture. This article sets out a framework for model driven engineering, which can be used as a point of reference for activity in this area. It proposes an organisation of the modelling 'space' and how to locate models in that space. It discusses different kinds of mappings between models. It explains why process and architecture are tightly connected. It discusses the importance and nature of tools. It identifies the need for defining families of languages and transformations, and for developing techniques for generating/configuring tools from such definitions. It concludes with a call to align metamodelling with formal language engineering techniques.

Model Driven Engineering

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

Summary) The abstract should follow the structure of the article (relevance, degree of exploration of the problem, the goal, the main results, conclusion) and characterize the theoretical and practical significance of the study results. The abstract should not contain wording echoing the title, cumbersome grammatical structures and abbreviations. The text should be written in scientific style. The volume of abstracts (summaries) depends on the content of the article, but should not be less than 250 words. All abbreviations must be disclosed in the summary (in spite of the fact that they will be disclosed in the main text of the article), references to the numbers of publications from reference list should not be made. The sentences of the abstract should constitute an integral text, which can be made by use of the words “consequently”, “for example”, “as a result”. Avoid the use of unnecessary introductory phrases (eg, “the author of the article considers...”, “The article presents...” and so on.)

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Ministry of Education and Science of the Russian Federation

IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society

A methodology for modifying VHDL descriptions is the core of this paper. Modifications are performed on general RTL descriptions composed of a mix of control and computation, that is, the typical type of description used for designing at the RT level. Such VHDL descriptions are automatically partitioned into a reference model composed of a controller driving a data-path. We call this transformation "VHDL restructuring". A set of restructuring steps is presented aiming at partitioning any VHDL description while guaranteeing the semantic equivalence of the restructured description with the original one. The main motivation to restructuring is the identification and separation of the two parts (FSM+data-path) which can thus be analyzed by using "ad hoc" synthesis, testability and design for testability algorithms. Promising results show that restructuring can sensibly impact on synthesis and testability.

Automatic VHDL restructuring for RTL synthesis optimization and testability improvement

The always increasing complexity of digital systems is overcome in design flows based on Transaction Level Modeling (TLM) by designing and verifying the system at different abstraction levels above RTL. The bottom-up approach is often adopted in the design flow when already existing RTL IPs are abstracted to be reused into the TLM system. In this context, proving the equivalence between a model and its abstracted version is still an open problem. In fact, traditional equivalence definitions and formal equivalence checking methodologies presented in the literature cannot be applied due to the very different internal characteristics of the models. In this paper, we propose a methodology based on simulation which gives two important contributes. Firstly, it relies on a suite of tools to automate as much as possible the equivalence verification process. Then, a more accurate definition of the equivalence concept is proposed by giving two quality measures of stimuli automatically generated for checking the equivalence between the generated TLM and the RTL golden model.

RTL-TLM equivalence checking based on simulation

This work presents a modeling and analysis framework for heterogeneous industrial networks architectures, which is based on a tight integration of a network simulator with embedded software, middleware and a real-time operating system. This framework is suitable for modeling and simulating the behavior of typical components involved in factory automation applications (e.g., PLCs, remote controllers, operational screens, etc.) when they are connected through heterogeneous industrial networks. Experiments show that the framework allows to take early architectural decisions by evaluating the expected system performance based on the available models.

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Software/network co-simulation of heterogeneous industrial networks architectures

Transaction Level Modeling (TLM) has been proposed as the leading strategy to address the always increasing complexity of digital systems design and verification. It allows designers to focus on the functionalities of the design, while abstracting away implementation details that will be added at lower abstraction levels. A TLM-based design flow can afford several advantages, such as, TLM-RTL mixed simulation, testbench and assertion reuse by exploiting the transactor concept. Nevertheless, transactors implementation and verification are duty of designers so far and their generation effort often overcomes the benefits of the TLM-based design adoption. In this paper a methodology is proposed to automate some parts of the transactor generation aiming at reaching their correct-by-construction implementation. The methodology relies on (i) the adoption a TLM API standard to ensure a correct refinement degree of transactors and (ii) the Extended Finite State Machine (EFSM) model to formally represent the communication environment through the generation process.

On the Automatic Transactor Generation for TLM-based Design Flows

The paper describes a functional ATPG that explores the DUT state space by exploiting an easy-to-traverse extended FSM model. The ATPG engine relies on learning, backjumping and constraint logic programming to deterministically generate test vectors for traversing all transitions of the EFSM

Franco Fummi

Papers

Automatic VHDL restructuring for RTL synthesis optimization and testability improvement

RTL-TLM equivalence checking based on simulation

Software/network co-simulation of heterogeneous industrial networks architectures

On the Automatic Transactor Generation for TLM-based Design Flows

FATE: a Functional ATPG to Traverse Unstabilized EFSMs