Mutation Testing is a fault-based software testing technique that has been widely studied for over three decades The literature on Mutation Testing has contributed a set of approaches, tools, developments, and empirical results This paper provides a comprehensive analysis and survey of Mutation Testing The paper also presents the results of several development trend analyses These analyses provide evidence that Mutation Testing techniques and tools are reaching a state of maturity and applicability, while the topic of Mutation Testing itself is the subject of increasing interest

An Analysis and Survey of the Development of Mutation Testing

The Object Management Group's (OMG) Model Driven Architecture (MDA) strategy envisages a world where models play a more direct role in software production, being amenable to manipulation and transformation by machine. Model Driven Engineering (MDE) is wider in scope than MDA. MDE combines process and analysis with architecture. This article sets out a framework for model driven engineering, which can be used as a point of reference for activity in this area. It proposes an organisation of the modelling 'space' and how to locate models in that space. It discusses different kinds of mappings between models. It explains why process and architecture are tightly connected. It discusses the importance and nature of tools. It identifies the need for defining families of languages and transformations, and for developing techniques for generating/configuring tools from such definitions. It concludes with a call to align metamodelling with formal language engineering techniques.

Model Driven Engineering

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

Summary) The abstract should follow the structure of the article (relevance, degree of exploration of the problem, the goal, the main results, conclusion) and characterize the theoretical and practical significance of the study results. The abstract should not contain wording echoing the title, cumbersome grammatical structures and abbreviations. The text should be written in scientific style. The volume of abstracts (summaries) depends on the content of the article, but should not be less than 250 words. All abbreviations must be disclosed in the summary (in spite of the fact that they will be disclosed in the main text of the article), references to the numbers of publications from reference list should not be made. The sentences of the abstract should constitute an integral text, which can be made by use of the words “consequently”, “for example”, “as a result”. Avoid the use of unnecessary introductory phrases (eg, “the author of the article considers...”, “The article presents...” and so on.)

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Ministry of Education and Science of the Russian Federation

IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society

The paper presents a system level co-simulation methodology for modeling, validating, and analyzing the performance of embedded systems. The proposed solution relies on the integration between an instruction set simulator (ISS) and the SystemC simulation kernel. In this way, the ISS is used to abstract the model of the real programmable device where the SW should run, while SystemC is used to model HW components that interact with the SW. A correct validation of such an architecture is infeasible without taking care of timing information. Thus, the paper proposes an effective timing synchronization mechanism, which uses timing information of an ISS (or a board) to synchronize the SystemC simulation.

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A timing-accurate HW/SW co-simulation of an ISS with SystemC

SystemC is a widespread language for HW/SW system simulation and design exploration, and thus a key development platform in embedded system design. However, the growing complexity of SoC designs is having an impact on simulation performance, leading to limited SoC exploration potential, which in turns affects development and verification schedules and time-to-market for new designs. Previous efforts have attempted to parallelize SystemC simulation, targeting both multiprocessors and GPUs. However, for practical designs, those approaches fall far short of satisfactory performance. This paper proposes SAGA, a novel simulation approach that fully exploits the intrinsic parallelism of RTL SystemC descriptions, targeting GPU platforms. By limiting synchronization events with ad-hoc static scheduling and separate independent dataflows, we shows that we can simulate complex SystemC descriptions up to 16 times faster than traditional simulators.

/pdf/saga-systemc-acceleration-on-gpu-architectures-4adt3z0d1s.pdf

SAGA: SystemC acceleration on GPU architectures

On behalf of the IEEE/ACM International Conference on Hardware/Software-Codesign and System Synthesis (CODES+ISSS) Technical Program Committee, we would like to welcome you to the 10th CODES+ISSS. The CODES+ISSS is the premier conference for system-level synthesis and design ranging from embedded systems to large-scale systems and beyond, systems of systems, with a focus on the design of hardware, software, and tools. In 2012, we continue the tradition of maintaining a high-quality forum for active discussion on current and innovative topics on system synthesis and design that bring together the latest in academic and industrial research and development.

We carried out a rigorous review process and a face-to-face Technical Program Committee meeting and selected 48 papers among 163 submissions with an acceptance rate of 29%. The Technical Program Committee carefully reviewed all papers with an average of 4 reviews per paper. The entire review process strictly obeyed the blind review policy, and the Technical Program Committee meeting was carefully conducted considering conflict of interest of the Technical Program Committee members. The Technical Program Committee members selected the a part of high-quality papers, and a part of high-quality papers were not accepted because this year CODES+ISSS paper selection was highly competitive. As interaction between presenters and other conference attendees is extremely important in CODES+ISSS, we organize poster sessions during the last 30 minutes of every session to encourage extensive interaction among the speakers and audiences.

The CODES+ISSS is part of the growing Embedded Systems Week (ESWEEK) that has been positioned as the premier international event in embedded systems research and development. The CODES+ISSS is complemented by two other flagship sister conferences: EMSOFT (International Conference on Embedded Software) and CASES (International Conference on Compliers, Architecture and Synthesis for Embedded Systems). Registrants to ESWEEK may attend sessions in any of the three conferences. The technical programs of the three conferences, including keynotes, special sessions, panels, tutorials and workshops, have been carefully planned to avoid major overlaps and complement each other.

In 2012, the CODES+ISSS Technical Program Committee compose 16 regular sessions, one of which is a joint session with the CASES Program Committee, two special sessions, and three tutorials. We implemented a two-stage selection process of the special sessions again in 2012. Special session proposals have been submitted to the Program Committee, presented and evaluated at the Program Committee meeting. We selected the best two proposals such as TLM verification and system-level design consisting of five contributions each. The special session paper presentation will be followed by a panel discussion with the special sessions organizers. In addition, the CODES+ISSS Technical Program is completed by two tutorials organized in the context of ESWeek.

Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

An effective selection of the more suited IP-core, available for a particular design, should be based on some simulation sessions. However, simulation models cannot be close enough to the real models of the core to protect the intellectual property. This paper proposes a Web-CAD methodology for IP-core analysis based on a client/server simulation architecture. The core vendor can make available to the public even the core models used for core synthesis without disclosing IP information. On the other side, the core user can simulate the remote core in the local simulation environment in the same way a local library component is simulated. To achieve this result, some problems concerning the non equivalence of the event driven semantic and the message driven semantic have been analyzed and solved.

A Web-CAD methodology for IP-core analysis and simulation

This paper describes an efficient error simulator able to analyze functional VHDL descriptions. The proposed simulation environment can be based on commercial VHDL simulators. All components of the simulation environment are automatically built starting from the VHDL specification of the description under test. The effectiveness of the simulator has been measured by using a random functional test generator. Functional test patterns produce, on some benchmarks, a higher gate-level fault coverage than the fault coverage achieved by a very efficient gate-level test pattern generator. Moreover, functional test generation requires a fraction of the time necessary to generate test at the gate level. This is due to the possibility of effectively exploring the test patterns space since error simulation is directly performed at the VHDL level.

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Franco Fummi

Papers

A timing-accurate HW/SW co-simulation of an ISS with SystemC

SAGA: SystemC acceleration on GPU architectures

Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

A Web-CAD methodology for IP-core analysis and simulation

A VHDL error simulator for functional test generation