The Object Management Group's (OMG) Model Driven Architecture (MDA) strategy envisages a world where models play a more direct role in software production, being amenable to manipulation and transformation by machine. Model Driven Engineering (MDE) is wider in scope than MDA. MDE combines process and analysis with architecture. This article sets out a framework for model driven engineering, which can be used as a point of reference for activity in this area. It proposes an organisation of the modelling 'space' and how to locate models in that space. It discusses different kinds of mappings between models. It explains why process and architecture are tightly connected. It discusses the importance and nature of tools. It identifies the need for defining families of languages and transformations, and for developing techniques for generating/configuring tools from such definitions. It concludes with a call to align metamodelling with formal language engineering techniques.

Model Driven Engineering

Network Simulator NS2

For systems-on-chip (SoC) development, a predominant part of the design time is the simulation time. Performance evaluation and design space exploration of such systems in bit- and cycle-true fashion is becoming prohibitive. We propose a traffic generation (TG) model that provides a fast and effective network-on-chip (NoC) development and debugging environment. By capturing the type and the timestamp of communication events at the boundary of an IP core in a reference environment, the TG can subsequently emulate the core's communication behavior in different environments. Access patterns and resource contention in a system are dependent on the interconnect architecture, and our TG is designed to capture the resulting reactiveness. The regenerated traffic, which represents a realistic workload, can thus be used to undertake faster architectural exploration of interconnection alternatives, effectively decoupling simulation of IP cores and of interconnect fabrics. The results with the TG on an AMBA interconnect show a simulation time speedup above a factor of 2 over a complete system simulation, with close to 100 % accuracy.

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A Network Traffic Generator Model for Fast Network-on-Chip Simulation

Software accounts for more than 80% of embedded system development efforts, so software performance estimation is a very important issue in system design. Recently, source level simulation (SLS) has become a state-of-the-art approach for software simulation in system level design. However, the simulation accuracy relies on the mapping between source code and binary code, which can be destroyed by compiler optimizations. This drawback strongly limits the usability of this technique in practical system design. We introduce an approach to overcome this limitation by converting source code to a low level representation, called intermediate source code (ISC). ISC has accounted for most compiler optimizations and has a structure close to binary code, so it allows for accurate back-annotation of timing information from the binary level. To show the benefits of our approach, we present a quantitative comparison of the related techniques with the proposed one, using a set of benchmarks.

An efficient approach for system-level timing simulation of compiler-optimized embedded software

eCloudRFID - A mobile software framework architecture for pervasive RFID-based applications

In a system-level design flow, the transition from a high-level description entry implies the refinement from an untimed, unpartitioned description to a real architecture where applications are executed on a programmable device and interact with ad-hoc hardware components. Simulation of such architectures requires the capability of efficient co-simulation of a model of hardware with a model of the processor. This paper presents two co-simulation methodologies, based on SystemC as hardware modeling language and on an instruction set simulator (ISS) as a model of the processor. The first one works at the SystemC kernel level and exploits potentialities of the GNU suite, whereas the second uses features offered by the operating system running on the ISS. The two methodologies improve co-simulation performance with respect to state-of the art methods, and provide different trade-offs between the simplicity of the programming model, the modeling power, and co-simulation performance.

Native ISS-SystemC integration for the co-simulation of multi-processor SoC

The design of state-of-the-art, complex embedded systems requires the capability of modeling and simulating the complex networked environment in which such systems operate. This implies the availability of both a networking modeling environment and traditional system-level modeling capabilities. In this paper we present a modeling and simulation methodology based on a timing accurate integration of a system-level modeling language (SystemC) and a network simulation environment (NS-2). The efficiency of the proposed design environment has been demonstrated on a description of a 802.11 MAC layer.

/pdf/a-timing-accurate-modeling-and-simulation-environment-for-46eoz854te.pdf

A timing-accurate modeling and simulation environment for networked embedded systems

Networked embedded systems pose several challenges in the modeling, simulation, and design domains. The presence of the network, in particular, makes an already critical task such as HW/SW co-simulation even more complex, since a three-way (HW/SW/network) co-simulation and co-design capability is required. Modeling of networks and their interaction with hardware and software is thus key for an effective design methodology at early stages of the design flow. In this work, we present a HW/SW/network co-simulation and co-design methodology, based on the integration of heterogeneous simulation environments such as systemC and NS (network simulator). This methodology has been successfully applied to the design of a system-on-chip performing the fast path of IPv4 routing, allowing to explore different HW/SW allocation for different network configurations.

/pdf/heterogeneous-co-simulation-of-networked-embedded-systems-39gd6alcw8.pdf

Heterogeneous co-simulation of networked embedded systems

Modular design is an important requirement in modern embedded system design flows because of the widespread acceptance of new paradigms such as IP core reuse and platform-based design. Co-simulation frameworks must thus support modular design, since programmable devices, ad-hoc HW components, and the interconnect infrastructure must be easily interchangeable in order to allow design exploration while keeping the SW portion unchanged or only marginally changed. The proposed co-simulation framework implements such a modular approach to co-simulation by means of a novel paradigm in which HW models can be modified on the fly by keeping the SW parts unchanged. This is achieved through an ISS-centric co-simulation strategy in which modularity is provided in terms of (i) the replacement of HW components thanks to the use of a common interface based on the device address space, or (ii) the use of different ISS's, thanks to a re-configurable simulator. We demonstrate our approach onto an industrial-strength embedded application, showing that the proposed co-simulation strategy provides both high speed and accuracy.

ISS-centric modular HW/SW co-simulation

Designers of factory automation applications increasingly demand for tools for rapid prototyping of hardware extensions to existing systems and verification of resulting behaviors through hardware and software co-simulation. This work presents a framework for the timing-accurate co-simulation of HDL models and their verification against hardware and software running on an actual embedded device of which only a minimal knowledge of the current design is required. Experiments on real-life applications show that early architectural and design decisions can be taken by measuring the expected performance on the models realized using the proposed framework.

/pdf/virtual-hardware-prototyping-through-timed-hardware-software-1s8kb0fevx.pdf

Giovanni Perbellini

Papers

Native ISS-SystemC integration for the co-simulation of multi-processor SoC

A timing-accurate modeling and simulation environment for networked embedded systems

Heterogeneous co-simulation of networked embedded systems

ISS-centric modular HW/SW co-simulation

Virtual Hardware Prototyping through Timed Hardware-Software Co-Simulation