Showing papers by "Franz Kreupl published in 2000"

Carbon nanotube field effect transistor has two nanotubes spaced apart to prevent tunnel current between them

Abstract: The field effect transistor (100) has a first carbon nanotube (101), providing a source region, a channel region and a drain region and a second carbon nanotube (106), providing a gate region and supplied with a control voltage, for controlling the conductivity of the channel region. The nanotubes are spaced apart by a sufficient distance to prevent any tunnel current between them, e.g. the second nanotube is applied to an insulation layer (105) around the channel region provided by the first nanotube.

Method for producing a semiconductor memory component

Abstract: The invention relates to a method for producing a semiconductor memory component, in particular, a DRAM or FeRAM, comprising a silicon substrate. At least one memory capacitor is located on said substrate, comprising a lower electrode, upper electrode and a dielectric layer which lies between said electrodes and which consists, in particular, of a ferroelectric material. The lower electrode is insulated from the silicon substrate by a barrier layer, consisting in particular of a diffusion barrier or a diffusion barrier combined with adhesive layers to form a sandwich. Said adhesive layers consist, in particular, of Ir, IrO2, or IrO. The barrier layer is structured before the application of the memory capacitor, using a hard mask consisting in particular of SiO2, SiN, SiON. The hard mask layer which remains after structuration is removed by uncovering the structured barrier layer. The invention is characterised in that the structured barrier layer is embedded in SiO2, using CVD (Chemical Vapour Deposition) before the removal of the remaining mask layer and that the remaining mask layer is removed with the SiO2 embedding layer from the surface of the barrier layer, using a SiO2 CMP (Chemical Mechanical Polishing) process.

Method for producing an integrated circuit having at least one metalicized surface

Abstract: In order to fabricate a metallization plane with lines and contacts, four dielectric layers are applied to a substrate. Firstly, contact holes are etched through the top two dielectric layers into the underlying dielectric layer, the remaining thickness of the latter layer being essentially equal to the thickness of the top layer. Line trenches are subsequently etched selectively with respect to the first dielectric layer and the third dielectric layer, whose surfaces are uncovered essentially simultaneously. After the first dielectric layer and the third dielectric layer have been patterned, contacts and lines are produced in the contact holes and line trenches.

Elektronisches Bauelement, Verfahren zum Herstellen einer leitenden Verbindung in einem elektronischen Bauelelent und Verfahren zum Herstellen eines elektronischen Bauelements

Abstract: Ein elektronisches Bauelement weist eine erste leitende Schicht, eine nicht-leitende Schicht sowie eine zweite leitende Schicht auf. Durch die nicht-leitende Schicht ist ein Loch geatzt. In dem Loch ist eine Nanorohre vorgesehen, durch die die erste leitende Schicht mit der zweiten leitenden Schicht leitend verbunden ist.

Electronic storage element used in CMOS technology comprises carbon nanotubes arranged skew to each other or crossing each other so that an electrical coupling is produced between the tubes

Abstract: Electronic storage element (600) comprises first nanotubes (601) and second nanotubes (603) arranged skew to each other or crossing each other so that an electrical coupling is produced between one part of the first tubes and one part of the second tubes. It is possible to decide whether the tubes are electrically coupled to each other or not at their crossing points (605). An Independent claim is also included for a process for the production of an electronic storage element. Preferred Features: The nanotubes are carbon nanotubes. A dielectric is arranged between the first and second nanotubes. A layer system made up of a first silicon dioxide layer, a silicon nitride layer and a second silicon dioxide layer is arranged between the first and second nanotubes.

Artificial neuron comprises a transistor and a number of electrical contacts which can be contacted by the ends of nanostructures

Abstract: Artificial neuron (100) comprises a transistor (101) and a number of electrical contacts which can be contacted by the ends of nanostructures. A first connection (102) of the transistor is coupled to each end of the nanostructures. The nanostructures are preferably silicon nano-wires or carbon nano-tubes. The transistor is a MOSFET, a bipolar transistor or a MIFG transistor.

Analog-digital converter has second electrode as flexible element extending freely in one direction and detector of variable distance between first and second electrodes

Abstract: The device has at least one first and one second electrode, whereby the second electrode is a flexible element extending freely in one direction that is flexible in the direction of the first electrode, and a measurement signal detector for detecting a variable distance between the first and second electrodes. The distance varies on the basis off an electric field acting on the two electrodes.

Elektronisches Speicherelement und Verfahren zum Herstellen eines elektronischen Speicherelements

Abstract: Eine Vielzahl von ersten Nanorohren und eine Vielzahl von zweiten Nanorohren sind zueinander windschief oder einander kreuzend angeordnet. Die Anordnung der Nanorohren erfolgt derart, dass eine elektrische Kopplung zwischen zumindest einem Teil der ersten Nanorohren und zumindest einem Teil der zweiten Nanorohren moglich ist in einer Weise, dass unterscheidbar ist, ob die ersten Nanorohren und die zweiten Nanorohren an ihren jeweiligen Kreuzungsstellen miteinander elektrisch gekoppelt sind oder nicht.

Field effect transistor comprises an electrically non-conducting substrate, a channel region between source and drain regions, and a gate region for controlling the channel region

Abstract: Field effect transistor comprises an electrically non-conducting substrate (101); a drain region; a source region; a channel region between the source an drain regions; and a gate region for controlling the channel region. The channel region has a metal layer (104). An Independent claim is also included for a process for the production of a field effect transistor comprising forming a source and a drain region on a substrate (101); applying a metal layer (104) which forms a channel region between the source and drain regions; forming a separating layer (107) on the metal layer and between the source and drain regions; and forming a gate region on the separating layer. Preferred Features: The metal layer is made from Pt, Au, Ag, Ti, Ta, Pd, Bi, In, Cr, V, Mn, Fe, Co, Ni, Y, Zr, Nb, Mo, Te, Hf, W or their alloys.

Electronic component, method for producing a conductive connection in an electronic Bauelelent and method for fabricating an electronic device

Abstract: Ein elektronisches Bauelement weist eine erste leitende Schicht, eine nicht-leitende Schicht sowie eine zweite leitende Schicht auf. Durch die nicht-leitende Schicht ist ein Loch geatzt. In dem Loch ist eine Nanorohre vorgesehen, durch die die erste leitende Schicht mit der zweiten leitenden Schicht leitend verbunden ist.