Energy harvesting generators are attractive as inexhaustible replacements for batteries in low-power wireless electronic devices and have received increasing research interest in recent years. Ambient motion is one of the main sources of energy for harvesting, and a wide range of motion-powered energy harvesters have been proposed or demonstrated, particularly at the microscale. This paper reviews the principles and state-of-art in motion-driven miniature energy harvesters and discusses trends, suitable applications, and possible future developments.

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Energy Harvesting From Human and Machine Motion for Wireless Electronic Devices

The electroencephalogram (EEG) is a classic noninvasive method for measuring a person's brain waves and is used in a large number of fields: from epilepsy and sleep disorder diagnosis to brain-computer interfaces (BCIs). Electrodes are placed on the scalp to detect the microvolt-sized signals that result from synchronized neuronal activity within the brain. Current long-term EEG monitoring is generally either carried out as an inpatient in combination with video recording and long cables to an amplifier and recording unit or is ambulatory. In the latter, the EEG recorder is portable but bulky, and in principle, the subject can go about their normal daily life during the recording. In practice, however, this is rarely the case. It is quite common for people undergoing ambulatory EEG monitoring to take time off work and stay at home rather than be seen in public with such a device. Wearable EEG is envisioned as the evolution of ambulatory EEG units from the bulky, limited lifetime devices available today to small devices present only on the head that can record EEG for days, weeks, or months at a time. Such miniaturized units could enable prolonged monitoring of chronic conditions such as epilepsy and greatly improve the end-user acceptance of BCI systems. In this article, we aim to provide a review and overview of wearable EEG technology, answering the questions: What is it, why is it needed, and what does it entail? We first investigate the requirements of portable EEG systems and then link these to the core applications of wearable EEG technology: epilepsy diagnosis, sleep disorder diagnosis, and BCIs. As a part of our review, we asked 21 neurologists (as a key user group) for their views on wearable EEG. This group highlighted that wearable EEG will be an essential future tool. Our descriptions here will focus mainly on epilepsy and the medical applications of wearable EEG, as this is the historical background of the EEG, our area of expertise, and a core motivating area in itself, but we will also discuss the other application areas. We continue by considering the forthcoming research challenges, principally new electrode technology and lower power electronics, and we outline our approach for dealing with the electronic power issues. We believe that the optimal approach to realizing wearable EEG technology is not to optimize any one part but to find the best set of tradeoffs at both the system and implementation level. In this article, we discuss two of these tradeoffs in detail: investigating the online compression of EEG data to reduce the system power consumption and the optimal method for providing this data compression.

Wearable electroencephalography. What is it, why is it needed, and what does it entail?

An operational transconductance amplifier (OTA) is a major building block and consumes most of the power in switched-capacitor (SC) circuits, but it is difficult to design low-voltage OTAs in scaled CMOS technologies. Instead of using an OTA, this paper proposes an inverter-based SC circuit and its application to low-voltage, low-power delta-sigma (DeltaSigma) modulators. Detailed analysis and design optimizations are also provided. Three inverter-based DeltaSigma modulators are implemented for an implantable pacemaker, a CMOS image sensor, and an audio codec. The modulator-I for an implantable pacemaker achieves 65-dB peak-SNDR for 120-Hz bandwidth consuming 0.73 muW with 1.5 V supply. The modulator-II for a CMOS image sensor implemented with 320-channel parallel ADC architecture achieves 63-dB peak-SNDR for 8-kHz bandwidth consuming 5.6 muW for each channel with 1.2-V supply. The modulator-III for an audio codec achieves 81-dB peak-SNDR with 20-kHz bandwidth consuming 36 muW with 0.7-V supply. The prototype DeltaSigma modulators achieved high power efficiency maintaining sufficient performances for practical applications.

Low Voltage, Low Power, Inverter-Based Switched-Capacitor Delta-Sigma Modulator

The electronics of a general biomedical device consist of energy delivery, analog-to-digital conversion, signal processing, and communication subsystems. Each of these blocks must be designed for minimum energy consumption. Specific design techniques, such as aggressive voltage scaling, dynamic power-performance management, and energy-efficient signaling, must be employed to adhere to the stringent energy constraint. The constraint itself is set by the energy source, so energy harvesting holds tremendous promise toward enabling sophisticated systems without straining user lifestyle. Further, once harvested, efficient delivery of the low-energy levels, as well as robust operation in the aggressive low-power modes, requires careful understanding and treatment of the specific design limitations that dominate this realm. We outline the performance and power constraints of biomedical devices, and present circuit techniques to achieve complete systems operating down to power levels of microwatts. In all cases, approaches that leverage advanced technology trends are emphasized.

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Ultralow-Power Electronics for Biomedical Applications

A fully integrated, programmable mixed-signal transceiver comprising a radio frequency integrated circuit (RFIC) which is frequency and protocol agnostic with digital inputs and outputs, the transceiver being programmable and configurable for multiple radio frequency bands and standards and being capable of connecting to many networks and service providers. The RFIC does not use spiral inductors and instead includes transmission line inductors allowing for improved scalability. Components of the transceiver are programmable to allow the transceiver to switch between different frequency bands of operating. Frequency switching can be accomplished though the content of digital registers coupled to the components.

Programmable radio transceiver

A successive approximation analog-to-digital converter (ADC) is presented operating at ultralow supply voltages. The circuit is realized in a 0.18-/spl mu/m standard CMOS technology. Neither low-V/sub T/ devices nor voltage boosting techniques are used. All voltage levels are between supply voltage V/sub DD/ and ground V/sub SS/. A passive sample-and-hold stage and a capacitor-based digital-to-analog converter are used to avoid application of operational amplifiers, since opamp operation requires higher values for the lowest possible supply voltage. The ADC has signal-to-noise-and-distortion ratios of 51.2 and 43.3 dB for supply voltages of 1 and 0.5 V, at sampling rates of 150 and 4.1 kS/s and power consumptions of 30 and 0.85 /spl mu/W, respectively. Proper operation is achieved down to a supply voltage of 0.4 V.

A 0.5-V 1-/spl mu/W successive approximation ADC

Excess loop delay (ELD) is well known for its detrimental effect on the performance and stability of continuous-time sigma-delta modulators. A detailed analysis on the most recently published compensation techniques for single-stage modulators is performed in this paper, thus enabling their application to an arbitrary modulator. Based on different characteristics such as circuit complexity, achievable dynamic range, or requirements on the operational amplifiers, their advantages and disadvantages are investigated. Subsequently, the analysis is extended to cascaded modulators. Contrary to intuition, the results indicate that a compensation of ELD in every stage of the cascade is insufficient for optimal performance. Although not configured in a feedback configuration and as such not suffering from stability problems, each coupling network between two stages must additionally be compensated for ELD.

A Comparative Study on Excess-Loop-Delay Compensation Techniques for Continuous-Time Sigma–Delta Modulators

A successive approximation analog-to-digital converter (ADC) is presented operating at ultra low supply voltages. The circuit is realized in a 0.18∝m CMOS technology. Neither low-VT devices nor voltage boosting techniques are used. All voltage levels are between supply voltage (VDD) and ground (VSS). A passive sample-and-hold stage and an capacitor-based digital-to-analog converter (DAC) are used to avoid application of opamps, since opamp operation requires higher values for the lowest possible supply voltage. The ADC has a signal-to-noiseand-distortion ratio (SNDR) of 51.2dB and 43.3dB for supply voltages of 1V and 0.5V, at sampling rates of 150kS/s and 4.1kS/s and power consumptions of 30∝W and 0.85∝W, respectively. Proper operation is achieved down to a supply voltage of 0.4V.

http://ieeexplore.ieee.org/iel5/9921/31530/01471512.pdf

A 0.5V, 1∝W Successive Approximation ADC

A 0.7-V MOSFET-only /spl Sigma//spl Delta/ modulator for voice band applications is presented. The second-order modulator is realized using a switched-opamp technique. All capacitors are realized using compensated MOS devices operated in the depletion region. A combination of parallel and series compensated depletion-mode MOSCAPs is used to obtain high area efficiency. The circuit is fabricated in a 0.18-/spl mu/m CMOS process. The only components used are standard n-MOS and p-MOS transistors with threshold voltages of approximately 400 mV. All transistors are operated within the supply voltage window of 0.7 V; voltage boosting techniques are not used. The active area is 0.082 mm/sup 2/. The modulator achieves 67-dB signal-to-noise-and-distortion ratio, 70-dB signal-to-noise ratio, and 75-dB dynamic range at 8-kHz signal bandwidth and consumes 80 /spl mu/W of power.

A 0.7-V MOSFET-only switched-opamp /spl Sigma//spl Delta/ modulator in standard digital CMOS technology

A low-voltage high-linearity MOSFET-only /spl Sigma//spl Delta/ modulator for speech band applications is presented. The modulator uses substrate biased MOSFETs in the depletion region as capacitors, linearized by a series compensation technique. A second-order fully differential single-loop architecture has been realized in a conventional 0.25-/spl mu/m digital n-well CMOS process without extra layers for capacitors. An SNDR of 72 dB and an SNR of 77 dB is obtained with 8-kHz signal bandwidth at an oversampling ratio of 64. The circuit consumes about 1 mW from a single 1.8-V power supply and occupies a core area of 0.08 mm/sup 2/.

Jens Sauerbrey

Papers

A 0.5-V 1-/spl mu/W successive approximation ADC

A Comparative Study on Excess-Loop-Delay Compensation Techniques for Continuous-Time Sigma–Delta Modulators

A 0.5V, 1∝W Successive Approximation ADC

A 0.7-V MOSFET-only switched-opamp /spl Sigma//spl Delta/ modulator in standard digital CMOS technology

A 1.8-V MOSFET-only /spl Sigma//spl Delta/ modulator using substrate biased depletion-mode MOS capacitors in series compensation