This brief presents a novel architecture for memory-based fast Fourier transform (FFT) computation for real-valued signals based on radix-2 decimation-in-frequency algorithm. A superior strategy of stage partition for the real FFT (RFFT) is proposed to minimize the computation clock cycles and maximize the utilization of the processing element (PE). The PE employed in our RFFT architecture can process four inputs in parallel by using two radix-2 butterflies and only two multiplexers. The proposed memory-addressing scheme and control of the multiplexers can be expressed in terms of a counter according to the RFFT computation stage. Furthermore, the proposed RFFT architecture can support more PEs in two dimensions as well. Compared with prior works, the proposed RFFT processors have the advantages of fewer computation cycles and lower hardware usage. The experiment shows that the proposed processor reduces the computation cycles by a factor of 17.5% for a 32-point RFFT computation compared with a recently presented work while maintaining lower hardware usage and complexity in the PE design.

A Novel Memory-Based FFT Architecture for Real-Valued Signals Based on a Radix-2 Decimation-In-Frequency Algorithm

A high-throughput programmable fast Fourier transform (FFT) processor is designed supporting 16- to 4096-point FFTs and 12- to 2400-point discrete Fourier transforms (DFTs) for 4G, wireless local area network, and future 5G. A 16-path data parallel memory-based architecture is selected as a tradeoff between throughput and cost. To implement a hardware-efficient high-speed processor, several improvements are provided. To maximally reuse the hardware resource, a reconfigurable butterfly unit is proposed to support computing including eight radix-2 in parallel, four radix-3/4 in parallel, two radix-5/8 in parallel, and a radix-16 in one clock cycle. Twiddle factor multipliers using different schemes are optimized and compared, wherein modified coordinate rotation digital computer scheme is finally implemented to minimize the hardware cost while supporting both FFTs and DFTs. An optimized conflict-free data access scheme is also proposed to support multiple butterflies at any radices. The processor is designed as a general IP and can be implemented using a processor synthesizer (application-specific instruction-set processor designer). The electronic design automation synthesis result based on a 65-nm technology shows that the processor area is 1.46 mm2. The processor supports 972 MS/s 4096-point FFT at 250 MHz with a power consumption of 68.64 mW and a signal-to-quantization-noise ratio of 66.1 dB. The proposed processor has better-normalized throughput per area unit than the state-of-the-art available designs.

A High-Flexible Low-Latency Memory-Based FFT Processor for 4G, WLAN, and Future 5G

This paper presents a multimode memory-based Fast Fourier Transform (FFT) processor for a medical system aimed at Fourier-domain optical coherence tomography (FD-OCT) capable of supporting wireless displays based on multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM). The proposed FFT processor enables the use of 2-stream 4096/2048/1024-point FFTs and 1- to 4-stream 128/64-point FFTs for FD-OCT and OFDM applications, respectively. Using cost-effective four-bank single-port SRAM operating in four-word data width, the proposed design provides data access for up to sixteen memory paths. In conjunction with a proposed FFT kernel devised using hardware-efficient multiplication and cache units, the proposed system allows high-throughput multimode FFT operations in an energy- and area-efficient configuration. A test chip was designed using TSMC-0.18 μm CMOS technology with a core size of 4.8 mm
 2
. Post-layout simulation performing 4096-point FFT at 80 MHz and the 128-point FFT at 40 MHz achieved throughput of 152 MS/s and 160 MS/s with power consumption of 156.2 mW and 69.9 mW, respectively. Compared to the previous approaches fully or partially supporting the specified OCT/OFDM FFTs, different degrees of area or energy efficiency improvements can be shown by our design depending on the FFT operation mode. In addition, system-level verification for practical OCT imaging was also performed using an FPGA platform.

Multimode Memory-Based FFT Processor for Wireless Display FD-OCT Medical Systems

Provided is a wireless probe including: an ultrasound reception/transmission module that receives a first power and scans a target object by transmitting ultrasound signals to the target object and receiving ultrasound echo signals reflected from the target object; a signal processing module that receives a second power, generates pulses for generating the ultrasound signals and generates ultrasound data by using the ultrasound echo signals; a wireless communication module that receives a third power and receives/transmits predetermined data from/to a medical device; a controller that controls supply of at least one of the first power, the second power, and the third power based on an operation state of the wireless probe; and a power unit that supplies or blocks the at least one of the first power, the second power, and the third power according to control of the controller. Each component included in the wireless probe may reduce power consumed by the wireless probe.

Wireless probe and method for power controlling of wireless probe

The scheduling of data access plays a prominent part in a memory-based fast Fourier transform (FFT) processor. In this article, a conflict-free data-access scheme is proposed and applied to implement a radix- $2^{k}$ FFT processor with the computing parallelism being the power of 2. The proposed FFT module exploits single-port RAMs to retain the area efficiency, and it has the following hardware-friendly features. First, the memories are merged into four banks under the arbitrary computing parallelism, which helps to circumvent the complicated data-routing circuit. Second, the parallelism of the input/output (I/O) data can be enlarged to the internal computing parallelism, which accelerates the data update and enhances the throughput capability. Furthermore, the concurrent I/O operation that overlaps the storage of the FFT input with the supply of FFT output in the same memory sets is allowed, which minimizes the memory occupation for the management of continuous data flow. Based on the testing on the field-programmable gate array (FPGA) and ASIC implementation using the SMIC 40-nm CMOS technology, it is demonstrated that the proposed FFT processor can offer high throughput and simultaneously achieve remarkable area and power efficiency.

Scheduling of Data Access for the Radix-2k FFT Processor Using Single-Port Memory

A single chip includes an analog module, an ultrasound imaging module, a wireless network module, a switch circuit and a central processing unit (CPU). The ultrasound imaging module controls an ultrasound front end, and the wireless network module controls a radio-frequency (RF) front end. The CPU controls the switch circuit to electrically connect the analog module to the ultrasound imaging circuit or the wireless network module.

Single chip and handheld electronic device

This paper presents a dual-application FFT processor for spectral domain optical coherence tomography (SD-OCT) systems integrated with a wireless local area networking (WLAN) module. A high-radix multimode FFT kernel together with the four-path memory-data access scheme is proposed to improve the hardware efficiency. By the proposed memory-based architecture, multimode 2048/1024-point FFT×2 (for SD-OCT) or 128/64-point FFT×4 (for WLAN) can be performed in an energy-efficient manner. A test chip has been designed using a TSMC 0.18µm process with a core area of 4.12 mm2. Through post-layout simulation, the power consumption is 69.2 mW and 72.7 mW at 40 MHz for OCT/2048-point FFT×2 and WLAN/128-point FFT×4 modes, respectively. Compared to the referred, the power saving of 26%∼53% can be achieved using the proposed design.

Fu-Chiang Jan

Papers

Multimode Memory-Based FFT Processor for Wireless Display FD-OCT Medical Systems

Single chip and handheld electronic device

A dual-application low-power FFT processor for WLAN-integrated SD-OCT systems