Miniaturization has steadily increased the economic usefulness of digital electronics through the past two decades. A variety of physical arguments are brought to bear on the question of how far miniaturization can be extended. The implications of the laws of quantum mechanics and thermodynamics for information storage are examined. The need for power dissipation in electrical information processing is demonstrated and the limits set on miniaturization by the problems of removing the heat thereby produced are estimated. limits with origins in properties of the materials used to make electronic devices are reviewed. The potential performance of various technologies based on nonsemiconductor phenomena is estimated and compared with the limits found for planar silicon technology. Attempts are made to guess at all of the many unknown parameters that enter into broadly applicable quantitative expressions of the properties of logic circuitry so that actual values of the limits can be estimated.

Physical limits in digital electronics

Drain-induced barrier lowering (DIBL) determines the ultimate proximity of surface diffusions and qualifies as one of the fundamental electrical limitations for VLSI. The important design parameters relating to DIBL are investigated using a numerical two-dimensional model, and a simple conceptual model is introduced as an aid for understanding the results. Under normal operating conditions of an IGFET, DIBL produces surface (rather than bulk) injection at the source. Comparison of a base case with a scaled design reveals that simple linear scaling by itself is insufficient for holding DIBL to a tolerable amount.

VLSI limitations from drain-induced barrier lowering

This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

The purpose of this review article is to report on the recent developments and the performance level achieved in the strained-Si/SiGe material system. In the first part, the technology of the growth of a high-quality strained-Si layer on a relaxed, linear or step-graded SiGe buffer layer is reviewed. Characterization results of strained-Si films obtained with secondary ion mass spectroscopy, Rutherford backscattering spectroscopy, atomic force microscopy, spectroscopic ellipsometry and Raman spectroscopy are presented. Techniques for the determination of bandgap parameters from electrical characterization of metal-oxide-semiconductor (MOS) structures on strained-Si film are discussed. In the second part, processing issues of strained-Si films in conventional Si technology with low thermal budget are critically reviewed. Thermal and low-temperature microwave plasma oxidation and nitridation of strained-Si layers are discussed. Some recent results on contact metallization of strained-Si using Ti and Pt are presented. In the last part, device applications of strained Si with special emphasis on heterostructure metal oxide semiconductor field effect transistors and modulation-doped field effect transistors are discussed. Design aspects and simulation results of n- and p-MOS devices with a strained-Si channel are presented. Possible future applications of strained-Si/SiGe in high-performance SiGe CMOS technology are indicated.

http://iopscience.iop.org/article/10.1088/0268-1242/13/11/002/pdf

Strained-Si heterostructure field effect transistors

Polysilicon thin film transistors (TFTs) differ from conventional silicon on insulator (SOI) transistors in that the TFT exhibits a fundamental gate length dependence of the voltage at which a kink occurs in the output characteristics. This difference is shown to be caused by the peak lateral electric field being strongly dependent on the doping density in an SOI transistor, but relatively insensitive to trap distribution in a TFT. Source barrier lowering which occurs in SOI transistors is absent in a TFT, where the increase in current is the result of a field redistribution along the channel. For very short gate lengths, the TFT exhibits a small pseudo-bipolar gain. Estimates of this bipolar gain can be made by simulation of TFT characteristics with and without impact ionisation. The magnitude of the gain is shown to be approximately inversely proportional to gate length.

A comparison of the kink effect in polysilicon thin film transistors and silicon on insulator transistors

A comprehensive investigation has been carried out into the factors which influence the maximum drain voltage of an M.O.S. transistor for normal pentode-like operation. The drain voltage is limited by two principal mechanisms, namely punch-through of the drain depletion region to the source, and breakdown, due to impact ionization in the high field region at the drain edge. A two-dimensional analysis technique for determining the drain voltage at the onset of either punch-through or avalanche breakdown, from a solution of Poisson's equation within the substrate depletion region, is described. The solutions are obtained using finite difference numerical methods which take into account the gate-induced potential profiles at the edge of the source and drain junctions. Boundary conditions of zero effective gate bias and channel current are imposed which simplify the solution of Poisson's equation to an electrostatic one. The punch-through voltage VPT is defined as the drain-to-source voltage at which the longitudinal field at any point along the edge of the source region inverts in sign to permit the drift of minority carriers from source to drain. Breakdown voltage, VBD, however, is determined by the drain voltage at which the maximum field in the device reaches the critical value for avalanche multiplication. Good agreement is achieved between theoretical and practical results for both mechanisms on a wide variety of devices. It is shown that VPT decreases as the channel length and substrate doping concentration decrease and as the oxide thickness and diffusion depth increase. VBD, however, decreases as the channel length, oxide thickness and diffusion depth decrease. Punch-through and breakdown are discussed for gate bias conditions above and below threshold. The sharp fall in breakdown voltage as the gate bias rises above threshold is explained on the basis of injected charge from the channel into the drain depletion region.

Drain voltage limitations of MOS transistors

A simulation study of a short-channel strained-Si p-MOSFET is presented An analytical model for hole mobility enhancement in strained silicon has been used in a two-dimensional (2D) device simulator to evaluate the strain dependence of the drain current and transconductance Simulation results have been verified with experimental device results and the leverage of the strained-Si channel p-MOSFET over conventional Si p-MOSFETs is shown both at low temperature and room temperature Optimal confinement of holes within the strained silicon occurs for a graded Si 07 Ge 03 buffer cap thickness of 40 nm This layer structure gives rise to an enhancement in transconductance of up to 60%

Strained-Si channel heterojunction p-MOSFETs

A method of determining the distribution of injected carriers within the pinch-off region of an insulated-gate field-effect transistor is described. The analysis is based on two-dimensional solutions of both Poisson's Equation and the current continuity equation for minority carriers, within a small region adjacent to the drain junction. The effect of carrier velocity saturation in the pinch-off region, on the carrier density distribution is assessed. Regions of maximum field are determined. The magnitude of the maximum field within the device is shown to be dependent on the concentration gradient of impurities at the edge of the drain diffusion.

The distribution of mobile carriers in the pinch-off region of an insulated-gate field-effect transistor and its influence on device breakdown

The first book to deal with a broad spectrum of process and device design, and modelling issues related to semiconductor devices, bridging the gap between device modelling and process design using TCAD. Presents a comprehensive perspective of emerging fields and covers topics ranging from materials to fabrication, devices, modelling and applications. Aimed at research-and-development engineers and scientists involved in microelectronics technology and device design via Technology CAD, and TCAD engineers and developers.

G.A. Armstrong

Papers

A comparison of the kink effect in polysilicon thin film transistors and silicon on insulator transistors

Drain voltage limitations of MOS transistors

Strained-Si channel heterojunction p-MOSFETs

The distribution of mobile carriers in the pinch-off region of an insulated-gate field-effect transistor and its influence on device breakdown

Technology Computer Aided Design for Si, SiGe and GaAs Integrated Circuits