G. Giacomini

TL;DR: In this paper, the present status of the detector design for SuperB is described and four separate progress reports that, taken collectively, describe progress made on the SuperB Project since the publication of the Superb Conceptual Design Report in 2007 and the Proceedings of SuperB Workshop VI in Valencia in 2008.

TL;DR: In order to fully exploit the readout capabilities of the MAPS, a dedicated fast readout architecture performing on-chip data sparsification and providing the timing information for the hits has been implemented in the prototype chip “APSEL4D”, having 4096 pixels.

TL;DR: In this paper, a low material budget silicon demonstrator has been tested by the SLIM5 collaboration with 12 GeV/c protons at the PS-T9 beam line at CERN.

TL;DR: In this paper, the conceptual design of the Silicon Vertex Tracker for the S uper B Detector is presented, based on double-sided silicon strip detectors for the outer layers, with the addition of an innermost Layer 0 close to the interaction point, with low material budget and capable of sustaining a background rate of several MHz/cm2.

TL;DR: In this article, the authors proposed a new deep n-well (DNW) sensor with a full in-pixel signal processing chain: charge preamplifier, shaper, discriminator and latch.