Measurements of the equivalent parallel conductance of metal-insulator-semiconductor (MIS) capacitors are shown to give more detailed and accurate information about interface states than capacitance measurements. Experimental techniques and methods of analysis are described. From the results of the conductance technique, a realistic characterization of the Si–SiO 2 interface is developed. Salient features are: A continuum of states is found across the band gap of the silicon. Capture cross sections for holes and electrons are independent of energy over large portions of the band gap. The surface potential is subject to statistical fluctuations arising from various sources. The dominant contribution in the samples measured arises from a random distribution of surface charge. The fluctuating surface potential causes a dispersion of interface state time constants in the depletion region. In the weak inversion region the dispersion is eliminated by interaction between interface states and the minority carrier band. A single time constant results. From the experimentally established facts, equivalent circuits accurately describing the measurements are constructed.

The si-sio, interface – electrical properties as determined by the metal-insulator-silicon conductance technique

In very small electronic devices the alternate capture and emission of carriers at an individual defect site generates discrete switching in the device resistance—referred to as a random telegraph signal (RTS) The study of RTSs has provided a powerful means of investigating the capture and emission kinetics of single defects, has demonstrated the defect origins of low-frequency (1/ƒ) noise in these devices, and has provided new insight into the nature of defects at the Si/SiO2 interface

Noise in solid-state microstructures: A new perspective on individual defects, interface states and low-frequency (1/ƒ) noise

A method of determining the energy distribution of surface states at silicon-silicon dioxide interfaces by using low-frequency differential capacitance measurements of MOS structures is described. Low-frequency measurements make it possible to determine the silicon surface potential as a function of MOS voltage directly from the experimental data without requiring knowledge of the Si doping profile. No graphical differentiations are required to determine the surface state density from the experimental curves, and errors introduced by uncertainties in the silicon doping density are reduced. Also, it is shown that the measurements can be used to determine the relative lateral uniformity in the characteristics of the oxide and interface under the MOS field plate. Nonuniformities can result in large errors in the surface-state density derived from MOS capacitance measurements. Measurements are presented and interpreted for both n- and p-type silicon samples prepared by bias-growing the oxide in steam.

Surface states at steam-grown silicon-silicon dioxide interfaces

A qualitative discussion of the device operation is first given using three-dimensional energy band diagrams to show the significance of the diffusion current. The theoretical static I–V characteristics are the computed including both the diffusion and the drift currents, based on the one-dimensional and gradual channel model. Drain current saturation phenomena are evident in these exact solutions which are in good agreement with the calculations based on the bulk charge approximation and with the experimental data for the entire non-saturating and saturated ranges. The relative importance of the two current components along the length of the channel is illustrated. The effects of the diffusion current on the three more important low-frequency dynamic characteristics (the short-circuit gate capacitance, the transconductance, and the drain conductance) are discussed. The surface potential, the quasi-Fermi potential, the surface electric field and the surface carrier concentration along the channel are examined. The complete one-dimensional gradual channel model is inadequate to account for the large drain conductance observed in the saturation range, and it is shown that the electric field longitudinal to the channel current flow must be taken into account near the drain junction where it is larger than the transverse field due to the voltage applied to the gate electrode.

Effects of diffusion current on characteristics of metal-oxide (insulator)-semiconductor transistors☆

A quasi-static technique is discussed for obtaining the ‘low frequency’ thermal equilibrium MOS capacitance-voltage characteristics The method is based on a measurement of the MOS charging current in response to a linear voltage ramp, so that the charging current is directly proportional to the incremental MOS capacitance With this technique, surface potential and the surface state density can be obtained relatively simply and over a large part of the energy gap on a single sample, while also providing a direct test for the presence of gross nonuniformities in MOS structures This method has been used to determine the surface state distribution at the interface of a bias grown steam oxide and 10 ω-cm n -type silicon, and the results are compared with composite measurements using the conductance technique for a similar interface The sensitivity for surface state density measurements is estimated to be of the order of 10 10 states per cm 2 eV near mid-gap for 10 ω-cm silicon and improves with decreasing doping density Some applications and limitations are also briefly discussed

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A quasi-static technique for MOS C-V and surface state measurements

The trapping of electrons and holes at a semiconductor surface by traps located in the oxide adjacent to the semiconductor has been considered. It is shown that the effective capture cross section of an oxide trap viewed by a carrier at the semiconductor surface is reduced by a factor which increases exponentially with the distance the trap is located from the interface. A pseudo-Fermi function in this position variable is developed which gives the probability that a trap will be filled (or emptied) in a measurement time, T m . The trapping kinetics developed in the first part of the paper are applied to yield the full frequency and bias dependence of an MOS capacitor for an arbitrary spatial and energy trap distribution. Specific examples are given and the problem of voltage hysteresis is dealt with quantitatively. The conclusion is that very little information about the energy distribution and capture cross sections of the oxide traps is obtained from the analysis of MOS-capacitance curves.

The effects of oxide traps on the MOS capacitance

The physical phenomena associated with the frequency response of the surface inversion layer of an MOS capacitor are examined. It is shown that the equivalent circuit presented by Lehovec and Slobodskoy for an MOS capacitor in the depletion-inversion mode of operation may be simplified when the capacitor is biased in the heavy inversion layer mode. Further it is shown that an additional resistance, to account for generation-recombination in the depletion region, must be included. This new resistance dominates the response for silicon units, which is shown to be as low as I–5o cps at room temperature. Experimentally, there are at least two observations which cannot be explained by the first order one dimensional model on which these equivalent circuits are based. The frequency responses of complementary units, fabricated on almost identical p- and n-type silicon differ by orders of magnitude, it is typically in the range 1–100 cps for n-type units, but may be as high as 10 Mc/s for equivalent p-type units. In addition, pronounced hysteresis in the bias dependence of the capacitance of some p-type units has been observed. A second-order two dimensional model is proposed to explain these anomalies. This model includes an “external” inversion layer, surrounding the gate electrode, produced during the formation of the oxide. The gate inversion layer, in this model, is coupled to the bulk through an additional RC network, representing the external inversion layer, which is in parallel with the equivalent network of the first order model. An approximate analysis of this second order model predicts a frequency response which is in agreement with experiment. The possibility of charge migration on the surface of the oxide, which serves to decouple the gate inversion layer from the external inversion layer, can account for the hysteresis in the capacitance vs. bias characteristics observed in these units.

Physical limitations on the frequency response of a semiconductor surface inversion layer

For the use of the MOS capacitance method in the study of surface properties, various approximations and assumptions, of a purely conceptual and of an experimental nature, are usually made. These are not always justified. In this paper the applicability of this capacitance method for surface studies is examined critically. It is shown that this method is limited in its applicability and accuracy, and that, in most cases, it yields only the gross features of the surface states. If there are traps distributed spatially throughout the oxide, only an effective surface state distribution can be found, and this effective distribution may be interpreted ambiguously as due either to traps right at the interface, throughout the oxide, or both. Because the MOS capacitance consists essentially of the oxide capacitance in series with the semiconductor capacitances there is a practical lower limit on the magnitude of the semiconductor capacitance which can be measured. Together with difficulties in interpreting measurements in the inversion layer regime, this leads to a restriction on that portion of the forbidden gap in which states may be investigated. MOS capacitors, produced by thermal oxidation of silicon in either wet or dry oxygen, were examined by this method. It was found that, within experimental accuracy, and within the range of surface potential that can be covered by these measurements, the total number of occupied traps usually varies linearly with surface potential if it is assumed that all the traps are located right at the interface. However, these results can also be explained if it is assumed that the oxide contains a high density of low lying trap sites which are essentially uniformly distributed spatially throughout the oxide. In some specimens a monoenergetic trap level 0.7 eV below the conduction band and located at the interface was found.

Limitations of the MOS capacitance method for the determination of semiconductor surface properties

Consideration is given to the phenomenon of saturation of drain current in the insulated-gate field-effect transistor. The effect of limited carrier drift velocity in the transistor channel is evaluated, and a quantitative theory developed to predict behavior in such a region of current flow. It is shown that the "paradox" of complete pinch-off at the drain need not necessarily be resolved by postulating a limiting carrier velocity to explain drain-current saturation. It is found that saturation of drain current may be meaningfully ascribed to saturation of carrier velocity only for special cases, such as n -type germanium transistors, and, in addition, this current saturation is only to "first order." Detailed consideration is given to behavior of drain-current saturation, and the physical mechanisms controlling saturation drain resistance and voltage gain are discussed and compared. It is proposed that for high-resistivity substrates, electrostatic drain to channel feedback is dominant, whereas for low-resistivity substrates modulation of the length of the space-charge region at the drain is dominant. Experimental evidence is presented for silicon metal-oxide-semiconductor (MOS) transistors which indicates that the effect of the channel mobile charge on the field distribution in the drain space-charge region is negligible as compared to several sources of "fixed" charge. Based on this it is concluded that carrier mobility within this region does not play a significant role in determining device characteristics. Brief consideration is also given to the "constant-carrier-mobility" approximation for behavior in the source region of the channel. It is found that due to fairly strong surface region scattering in silicon units, the effects of field dependent mobility are reduced substantially below that observed in single-crystal bulk material. The constant-mobility approximation is also experimentally confirmed by the excellent "square-law behavior" demonstrated by these transistors.

Carrier mobility and current saturation in the MOS transistor

Quantum mechanical tunneling through insulating barriers has received considerable attention in recent years, especially in metal-insulator-metal systems and p − n junctions. It is the purpose of this paper to discuss tunneling in the MIS contact. In this paper we define the d.c. currents which flow and then calculate the voltage distribution in the contact. It is found that as long as the semiconductor spacecharge region is of the order of the insulator thickness (∼ 50 A) considerable voltage drops across the semiconductor. Using this, a voltage region of low conductance is shown to exist, over which the metal Fermi level is opposite the forbidden gap of the semiconductor. This region is shown to be greater than the semiconductor energy gap. In addition, the a.c. frequency dependent currents which flow in an MIS contact due to interface states are calculated. It is shown that interface states can contribute to the a.c. conductance via two mechanisms; time lag in trapping and recombination of carriers in the semiconductor bands and tunneling via interface states. Both of these mechanisms are discussed and the conditions under which one or the other make the major contribution to the a.c. conductance is analyzed.

G. Warfield

Papers

The effects of oxide traps on the MOS capacitance

Physical limitations on the frequency response of a semiconductor surface inversion layer

Limitations of the MOS capacitance method for the determination of semiconductor surface properties

Carrier mobility and current saturation in the MOS transistor

Tunneling in MIS structures—I. Theory