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Journal ArticleDOI

Limitations of the MOS capacitance method for the determination of semiconductor surface properties

K.H. Zaininger, +1 more
- 01 Apr 1965 - 
- Vol. 12, Iss: 4, pp 179-193
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TLDR
In this paper, the applicability of the MOS capacitance method for surface studies is examined critically, and it is shown that this method is limited in its applicability and accuracy, and that, in most cases, it yields only the gross features of the surface states.
Abstract
For the use of the MOS capacitance method in the study of surface properties, various approximations and assumptions, of a purely conceptual and of an experimental nature, are usually made. These are not always justified. In this paper the applicability of this capacitance method for surface studies is examined critically. It is shown that this method is limited in its applicability and accuracy, and that, in most cases, it yields only the gross features of the surface states. If there are traps distributed spatially throughout the oxide, only an effective surface state distribution can be found, and this effective distribution may be interpreted ambiguously as due either to traps right at the interface, throughout the oxide, or both. Because the MOS capacitance consists essentially of the oxide capacitance in series with the semiconductor capacitances there is a practical lower limit on the magnitude of the semiconductor capacitance which can be measured. Together with difficulties in interpreting measurements in the inversion layer regime, this leads to a restriction on that portion of the forbidden gap in which states may be investigated. MOS capacitors, produced by thermal oxidation of silicon in either wet or dry oxygen, were examined by this method. It was found that, within experimental accuracy, and within the range of surface potential that can be covered by these measurements, the total number of occupied traps usually varies linearly with surface potential if it is assumed that all the traps are located right at the interface. However, these results can also be explained if it is assumed that the oxide contains a high density of low lying trap sites which are essentially uniformly distributed spatially throughout the oxide. In some specimens a monoenergetic trap level 0.7 eV below the conduction band and located at the interface was found.

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Citations
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Journal ArticleDOI

The si-sio, interface – electrical properties as determined by the metal-insulator-silicon conductance technique

TL;DR: In this article, a realistic characterization of the Si-SiO 2 interface is developed, where a continuum of states is found across the band gap of the silicon, and the dominant contribution in the samples measured arises from a random distribution of surface charge.
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Surface states at steam-grown silicon-silicon dioxide interfaces

TL;DR: In this article, a method of determining the energy distribution of surface states at silicon-silicon dioxide interfaces by using low-frequency differential capacitance measurements of MOS structures is described.
Journal ArticleDOI

A quasi-static technique for MOS C-V and surface state measurements

TL;DR: In this paper, a quasi-static technique is proposed to obtain the thermal equilibrium MOS capacitance-voltage characteristics. The method is based on a measurement of the MOS charging current in response to a linear voltage ramp, so that the charging current is directly proportional to the incremental MOS capacity.
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Substrate crosstalk reduction using SOI technology

TL;DR: In this paper, the authors analyzed both by simulations and measurements the substrate crosstalk performances of various Silicon-On-Insulator (SOI) technologies, and compared them to those of normal bulk CMOS process.
References
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Journal ArticleDOI

An investigation of surface states at a silicon/silicon oxide interface employing metal-oxide-silicon diodes

TL;DR: In this article, the M-O-S diode was introduced, and a theory for its operation in the absence of surface states was obtained, and it was shown that surface states with non-zero relaxation times may increase the capacitance of the device, as well as affect the proportion of applied voltage which appears across the silicon.
Journal ArticleDOI

Physical limitations on the frequency response of a semiconductor surface inversion layer

TL;DR: In this article, the physical properties of the surface inversion layer of an MOS capacitance are examined and a second-order two-dimensional model is proposed to explain these anomalies.
Journal ArticleDOI

Semiconductor surface varactor

TL;DR: In this article, the performance of a thermally grown oxide on silicon was analyzed and measurements made on several experimental units were described, and a theory developed from the surface charge relation was shown to agree with the experimental data over a wide range of silicon resistivity.
Journal ArticleDOI

Field Effect-Capacitance Analysis of Surface States on Silicon

TL;DR: Capacitance measurements on silicon-silicon oxide-metal combinations are presented, and these indicate a quasi-continuous spectrum of surface states with a density of approximately 1 × 1012 states/cm2 · eV in the range 0.2 to 0.8 eV above the valence band for both, p-and n-type samples, and a total density of 1.7 × 1000 states/ cm2 as mentioned in this paper.
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