Gang Liu

TL;DR: An IF interface to the analog baseband is desired for low power consumption in the handset or user equipment (UE) active antenna and to enable use of arrays of transceivers for customer premises equipment (CPE) or basestation (BS) antenna arrays with a low-loss IF power-combining/splitting network implemented on an antenna backplane carrying multiple tiled antenna modules.

TL;DR: To the best of the authors' knowledge, both LNAs achieve the widest bandwidth in corresponding frequency bands with very competitive gain and NF.

Abstract: This paper presents frequency doublers with high output power for millimeter-wave applications. The circuits are fabricated using a 45nm SOI CMOS technology. A new circuit topology, combining a push-push doubler core with a cascaded stacked amplifier, has been implemented to increase the output power. The first doubler delivers 10.2 dBm peak power at 100 GHz output, with a 3-dB bandwidth from 88 to 104 GHz and DC-RF efficiency of 4.1%, while the second doubler has 5.2 dBm peak power at 202 GHz, with a 3-dB bandwidth from 180 to 212 GHz and DC-RF efficiency of 3.3%. To the authors' knowledge, these are the highest powers reported for silicon frequency doublers in similar frequency ranges to date. The 200 GHz doubler also provides the highest on-chip power from a single-element signal generation circuit without power combining.

TL;DR: A 28GHz phased array transceiver with RF/IF conversion in 28nm bulk CMOS supports up to 12 antenna elements each on 2 MIMO layers and implements an AMPM compensated PA, passive 3b phase shifters and supports tiling to extend the antenna array size for prototype basestation applications.

TL;DR: In this paper, the operation of a frequency quadrupler as a transmitter to accurately generate amplitude and phase-modulated signals is demonstrated, and a quadrupled memory polynomial (Q-MP) model is derived for forward modeling.