A fully-integrated 18.5 kHz RC time-constant-based oscillator is designed in 65 nm CMOS for sleep-mode timers in wireless sensors. A comparator offset cancellation scheme achieves $4\times $ to $25\times $ temperature stability improvement, leading to an accuracy of ±0.18% to ±0.55% over −40 to 90 °C. Sub-threshold operation and low-swing oscillations result in ultra-low power consumption of 130 nW. The architecture also provides timing noise suppression, leading to $10\times $ reduction in long-term Allan deviation. It is measured to have a stability of 20 ppm or better for measurement intervals over 0.5 s. The oscillator also has a fast startup-time, with the period settling in 4 cycles.

An RC Oscillator With Comparator Offset Cancellation

This paper proposes a 32.7 kHz self-biased wake-up timer using temperature-insensitive resistive current. A dual-loop structure with supply-regulation loop and frequency-locked loop determines the regulated voltages at both ends of a temperature-compensated resistor and cancels out the amplifier offset voltages, thus generating temperature-insensitive resistive current for the switched capacitor. Moreover, a self-biasing scheme in low-power design reduces the power variation across the temperature range and eliminates the necessity of a sub- $\mu \text{A}$ reference current generator. The proposed timer with its start-up circuit generates <12 ms lock time, which is 20 times less than what obtained without a start-up circuit, and exhibits a long-term frequency stability of 10 ppm and a temperature coefficient of 13.2 ppm/°C with an energy efficiency of 1.08 nW/kHz.

A 1.08-nW/kHz 13.2-ppm/°C Self-Biased Timer Using Temperature-Insensitive Resistive Current

This brief presents a low-power low-jitter relaxation oscillator for on-chip low-frequency clock generation. A dynamic common-gate comparator is proposed to reduce the power, combined with a slope boosting technique to reduce the period jitter. A peak-detecting feedback loop is implemented to maintain frequency stability over temperature variations. The oscillator achieves 0.025% period jitter and 70 ppm/°C temperature coefficient while consuming 1.36 $\mu \text{W}$ at 364 kHz with a 1.2-V supply.

Relaxation Oscillator With Dynamic Comparator and Slope-Boosting Technique

An on-chip frequency reference for built-in testing and calibration applications is presented. The design combines a proportional-to-absolute-temperature (PTAT) current reference and a relaxation oscillator core. A temperature compensation scheme is realized based on the thermal voltage, for which simulations indicate low sensitivity to process variations. The oscillator was designed and simulated in a 130nm CMOS process with a power supply of 1.2V. It generates a 40KHz output and occupies a layout area of 0.025mm2. A temperature coefficient of 101ppm/°C is achieved over the range from −30°C to 85°C. The simulated phase noise is −90dBc/Hz at 10KHz offset.

A low-power temperature-compensated relaxation oscillator for built-in test signal generation

This brief presents a self-calibration technique for on-chip precise clock generator used in the field of power electronics. In this technique, the operating frequency of the power grid is employed as the frequency reference to eliminate the frequency variation of the clock generator introduced by the fabrication process. To demonstrate the effectiveness of this technique, an on-chip relaxation oscillator has been designed, analyzed and verified with a 0.5- $\boldsymbol{\mu}\mbox{m}$ standard CMOS technology. Measurement results show the oscillator with self-calibration operates at a frequency of about 103.7 kHz and draws 90 $\boldsymbol{\mu}\mbox{A}$ current from a 5-V supply. 2.83% $(\mathbf{3}\boldsymbol{\sigma})$ frequency variation is achieved, which is more than 3× lower than the one without self-calibration.

A Self-Calibration Technique for On-Chip Precise Clock Generator

An on-chip frequency reference is designed for low-power, low-cost, and fully integrated system-on-chip designs. In this relaxation oscillator, pseudodifferential architecture is used to eliminate frequency variation caused by bias current, and interleaving capacitors are implemented to extend its discharge time. A low-leakage programmable switch array (PSA) trimming method is proposed to calibrate the first- and second-order temperature coefficients (TCs) of the composite resistor. The oscillator was fabricated in a 0.35-μm 2P4M CMOS process with an area of 0.162 mm2. The oscillator operates at 130 kHz, and measurement results show that it achieves a frequency variation of less than ±0.5% over a temperature range of -20 °C-100°C and less than ±0.4% over a supply voltage range of 1-3 V.

A $\pm$ 0.5% Precision On-Chip Frequency Reference With Programmable Switch Array for Crystal-Less Applications

According to one embodiment, the present invention includes a system that has a mechanical tuning mechanism to enable a user to select a radio channel, a variable resistance coupled to the mechanical tuning mechanism, and a radio receiver implemented on a die of a semiconductor package. The variable resistance has a first terminal to couple to a supply voltage and a second terminal to couple to a ground voltage, and a connection to provide a variable analog voltage responsive to the user selection. In turn, the receiver is coupled to receive the variable analog voltage via a first pin of the package, receive the supply voltage via a second pin of the package, and receive the ground voltage via a third pin of the package, in a single pin tuning mode. The receiver can downconvert a radio frequency (RF) signal to a second frequency signal with a mixing signal having a frequency based on the variable analog voltage.

Gang Yuan

Papers

A $\pm$ 0.5% Precision On-Chip Frequency Reference With Programmable Switch Array for Crystal-Less Applications

Providing analog tuning for a radio with a controllable number of pins