S
Sumeet Kumar Gupta
Researcher at Purdue University
Publications - 162
Citations - 3998
Sumeet Kumar Gupta is an academic researcher from Purdue University. The author has contributed to research in topics: Transistor & Non-volatile memory. The author has an hindex of 29, co-authored 147 publications receiving 2816 citations. Previous affiliations of Sumeet Kumar Gupta include Pennsylvania State University & Indian Institutes of Technology.
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Journal ArticleDOI
A steep-slope transistor based on abrupt electronic phase transition
Nikhil Shukla,Arun V. Thathachary,Ashish Agrawal,Hanjong Paik,Ahmedullah Aziz,Darrell G. Schlom,Sumeet Kumar Gupta,Roman Engel-Herbert,Suman Datta +8 more
TL;DR: A pathway for harnessing the abrupt resistivity transformation across the insulator-to-metal transition in vanadium dioxide (VO2) is demonstrated, to design a hybrid-phase-transition field-effect transistor that exhibits gate controlled steep (‘sub-kT/q') and reversible switching at room temperature.
Journal ArticleDOI
A ferroelectric semiconductor field-effect transistor
Mengwei Si,Atanu K. Saha,Shengjie Gao,Gang Qiu,Jing-Kai Qin,Yuqin Duan,Jie Jian,Chang Niu,Haiyan Wang,Wenzhuo Wu,Sumeet Kumar Gupta,Peide D. Ye +11 more
TL;DR: In this paper, a two-dimensional indium selenide (α-In2Se3) channel material was used as the channel material in the device, and a passivation method based on the atomic layer deposition of aluminium oxide (Al2O3) was developed.
Proceedings ArticleDOI
KNACK: A hybrid spin-charge mixed-mode simulator for evaluating different genres of spin-transfer torque MRAM bit-cells
Xuanyao Fong,Sumeet Kumar Gupta,Niladri Narayan Mojumder,Sri Harsha Choday,Charles Augustine,Kaushik Roy +5 more
TL;DR: In this article, the authors propose a simulation framework that captures device physics at the atomistic level when simulating spin-transfer torque MRAM at the bit-cell level using the Non-Equilibrium Green's Function (NEGF) formalism.
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Physics-Based Circuit-Compatible SPICE Model for Ferroelectric Transistors
TL;DR: In this article, a SPICE model for ferroelectric transistors (FEFETs) based on time-dependent Landau-Khalatnikov equation solved self-consistently with the transistor equations is presented.
Proceedings ArticleDOI
Future cache design using STT MRAMs for improved energy efficiency: devices, circuits and architecture
TL;DR: This work presents a cross-layer (device-circuit-architecture) approach to energy-efficient cache design using STT MRAM, and proposes microarchitectural techniques viz. sequential cache read and partial cache line update, which exploit the non-volatility of STTMRAM to further improve energy efficiency.