A MIMO radio transceiver to support processing of multiple signals for simultaneous transmission via corresponding ones of a plurality of antennas and to support receive processing of multiple signals detected by corresponding ones of the plurality of antennas. The radio transceiver provides, on a single semiconductor integrated circuit, a receiver circuit or path for each of a plurality of antennas and a transmit circuit or path for each of the plurality of antennas. Each receiver circuit downconverts the RF signal detected by its associated antenna to a baseband signal. Similarly, each transmit path upconverts a baseband signal to be transmitted by an assigned antenna.

Multiple-input multiple-output radio transceiver

The demand for radio frequency (RF) integrated circuits with reduced power consumption is growing owing to the trend toward system-on-a-chip (SoC) implementations in deep-sub-micron CMOS technologies. The concomitant need for high performance imposes additional challenges for circuit designers. In this paper, a g/sub m/-boosted common-gate low-noise amplifier (CGLNA), differential Colpitts voltage-controlled oscillators (VCO), and a quadrature Colpitts voltage-controlled oscillator (QVCO) are presented as alternatives to the conventional common-source LNA and cross-coupled VCO/QVCO topologies. Specifically, a g/sub m/-boosted common-gate LNA loosens the link between noise factor (i.e., noise match) and input matching (i.e., power match ); consequently, both noise factor and bias current are simultaneously reduced. A transformer-coupled CGLNA is described. Suggested by the functional and topological similarities between amplifiers and oscillators, differential Colpitts VCO and QVCO circuits are presented that relax the start-up requirements and improve both close-in and far-out phase noise compared to conventional Colpitts configurations. Experimental results from a 0.18-/spl mu/m CMOS process validate the g/sub m/-boosting design principle.

G/sub m/-boosted common-gate LNA and differential colpitts VCO/QVCO in 0.18-/spl mu/m CMOS

The invention provides an image display device that has an especially satisfactory display quality for animated images, and sufficiently suppresses the irregularities of display quality among pixels. The image display device includes a light emitting drive means that drives a light emitting means, based on an analog display signal inputted to the pixels, and a light emitting control switch for controlling a light-on or light-off of the light emitting means on one end of the light emitting drive means in each pixel.

Image Display Device

A transceiver for transmitting and receiving signals includes a transmitter operative to up-convert baseband signals from a baseband frequency into RF signals at a radio frequency (RF) frequency and output the RF signals, a receiver operative to receive RF signals and down-convert the RF signals into baseband signals having the baseband frequency, and a plurality of calibration paths coupling the transmitter to the receiver. Any of the calibration paths can be selected to be active when calibrating components of the transceiver. Tunable components can use calibration information to optimize transceiver performance.

Direct-conversion transceiver enabling digital calibration

A low-power CMOS reconfigurable analog-to-digital converter that can digitize signals over a wide range of bandwidth and resolution with adaptive power consumption is described. The converter achieves the wide operating range by (1) reconfiguring its architecture between pipeline and delta-sigma modes; (2) varying its circuit parameters, such as size of capacitors, length of pipeline, and oversampling ratio, among others; and (3) varying the bias currents of the opamps in proportion to the converter sampling frequency, accomplished through the use of a phase-locked loop (PLL). This converter also incorporates several power-reducing features such as thermal noise limited design, global converter chopping in the pipeline mode, opamp scaling, opamp sharing between consecutive stages in the pipeline mode, an opamp chopping technique in the delta-sigma mode, and other design techniques. The opamp chopping technique achieves faster closed-loop settling time and lower thermal noise than conventional design. At a converter power supply of 3.3 V, the converter achieves a bandwidth range of 0-10 MHz over a resolution range of 6-16 bits, and parameter reconfiguration time of twelve clock cycles. Its PLL lock range is measured at 20 kHz to 40 MHz. In the delta-sigma mode, it achieves a maximum signal-to-noise ratio of 94 dB and second and third harmonic distortions of 102 and 95 dB, respectively, at 10 MHz clock frequency, 9.4 kHz bandwidth, and 17.6 mW power. In the pipeline mode, it achieves a maximum DNL and INL of /spl plusmn/0.55 LSBs and /spl plusmn/0.82 LSBs, respectively, at 11 bits, at a clock frequency of 2.6 MHz and 1 MHz tone with 24.6 mW of power.

A low-power reconfigurable analog-to-digital converter

Issues associated with the integration of transceiver components on to a single silicon substrate are discussed. In particular, recently proposed receiver and transmitter architectures for high integration are examined on the promise of providing multistandard capability. In addition, existing barriers to lower power transceiver operation are examined as well as some proposed directions for future integrated transceiver research and development.

Recent developments in high integration multi-standard CMOS transceivers for personal communication systems

A receiver includes a Gilbert cell mixer comprising an input transconductance stage. The input transconductance stage includes first and second transistors receiving an input signal and providing a first gain characteristic that is substantially non-linear over an operating frequency range of the receiver. Third and fourth transistors receive the input signal and provide a second gain characteristic that is substantially non-linear over the operating range of the receiver. A combined gain characteristic of the input transconductance stage is based on the first and second gain characteristics and is substantially linear over the operating frequency range of the receiver.

Mixer gain calibration method and apparatus

A low noise amplifier includes an input stage. The input stage includes a first device configured to receive an input signal. A second device is connected to the first device. The second device has a predetermined input impedance. The input stage is configured so that a change in the input signal to the first device causes a linearly proportional change in a conductance of the first device. A voltage at a junction between the first device and the second device remains substantially constant due to the predetermined input impedance of the second device.

Method and apparatus for an LNA with high linearity and improved gain control

Systems and methods are provided for calibrating the control mechanism in a communication circuit to allow the communication circuit to maintain a desired output power level. The communication circuit includes a variable gain adjustment circuit and a power amplifier, which operate together to provide an output power level. A control circuit controls the variable gain adjustment circuit based on a default gain parameter, a high power threshold, and a low power threshold. A calibration circuit in the control circuit calibrates a default gain parameter to provide a desired output power. A power detector can detect the desired output power level to provide an output power measurement. The calibration circuit calibrates upper and lower power thresholds to provide an acceptable range of power variation around the output power measurement.

Systems and methods for calibrating power regulated communication circuitry

A transceiver including a transceiver component with a first and second inputs and an output. The transceiver is configured to (i) receive an input signal having packets via the first input and (ii) generate output signals at the output based on the input signal. The transceiver further includes a first comparator configured to compare the output signals and generate a first comparison signal; a register configured to store the first comparison signal; a calibration circuit is configured to generate a current signal based on the first comparison signal to adjust a current in the transceiver component; and a signal generator is configured to generate a reference signal based on the current signal. The transceiver component is configured to (i) based on the current signal, adjust a performance parameter of the transceiver at times synchronized with the packets and (ii) generate the output signals based on the current signal and the reference signal.

George Chien

Papers

Recent developments in high integration multi-standard CMOS transceivers for personal communication systems

Mixer gain calibration method and apparatus

Method and apparatus for an LNA with high linearity and improved gain control

Systems and methods for calibrating power regulated communication circuitry

Frame/packet-based calibration for wireless transceivers