This survey deals with 1/f noise in homogeneous semiconductor samples. A distinction is made between mobility noise and number noise. It is shown that there always is mobility noise with an /spl alpha/ value with a magnitude in the order of 10/sup -4/. Damaging the crystal has a strong influence on /spl alpha/, /spl alpha/ may increase by orders of magnitude. Some theoretical models are briefly discussed none of them can explain all experimental results. The /spl alpha/ values of several semiconductors are given. These values can be used in calculations of 1/f noise in devices. >

1/f Noise Sources

This paper provides evidence that, as a result of constant-field scaling, the peak f T (approx. 0.3 mA/μm), peak f MAX (approx. 0.2 mA/μm), and optimum noise figure NF MIN (approx. 0.15 mA/pm) current densities of Si and SOI n-channel MOSFETs are largely unchanged over technology nodes and foundries. It is demonstrated that the characteristic current densities also remain invariant for the most common circuit topologies such as MOSFET cascodes, MOS-SiGe HBT cascodes, current-mode logic (CML) gates, and nMOS transimpedance amplifiers (TIAs) with active pMOSFET loads. As a consequence, it is proposed that constant current-density biasing schemes be applied to MOSFET analog/mixed-signal/RF and high-speed digital circuit design. This will alleviate the problem of ever-diminishing effective gate voltages as CMOS is scaled below 90 nm, and will reduce the impact of statistical process variation, temperature and bias current variation on circuit performance. The second half of the paper illustrates that constant current-density biasing allows for the porting of SiGe BiCMOS cascode operational amplifiers, low-noise CMOS TIAs, and MOS-CML and BiCMOS-CML logic gates and output drivers between technology nodes and foundries, and even from bulk CMOS to SOI processes, with little or no redesign. Examples are provided of several record-setting circuits such as: 1) SiGe BiCMOS operational amplifiers with up to 37-GHz unity gain bandwidth; 2) a 2.5-V SiGe BiCMOS high-speed logic chip set consisting of 49-GHz retimer, 40-GHz TIAs, 80-GHz output driver with pre-emphasis and output swing control; and 3) 1-V 90-nm bulk and SOI CMOS TIAs with over 26-GHz bandwidth, less than 8-dB noise figure and operating at data rates up to 38.8 Gb/s. Such building blocks are required for the next generation of low-power 40-80 Gb/s wireline transceivers.

The invariance of characteristic current densities in nanoscale MOSFETs and its impact on algorithmic design methodologies and design porting of Si(Ge) (Bi)CMOS high-speed building blocks

This paper presents a SPICE-like graphene field-effect transistor (GFET) model with an improved carrier mobility analysis. The model considers the mobility difference between the electrons and the holes in graphene, as well as the mobility variation against the carrier density. Closed-form analytical solutions have been derived, and the model has been implemented in Verilog-A language. This was compiled into an advanced design system. The proposed model gives excellent agreement between the simulation results and the measurement data for both the hole and electron conduction simultaneously. The model is suitable for the exploration of GFET-based applications, especially for those using the ambipolar transfer property of GFET.

Graphene Field-Effect Transistor Model With Improved Carrier Mobility Analysis

We present a circuit-compatible compact model of the intrinsic capacitances of graphene field-effect transistors (GFETs). Together with a compact drain current model, a large-signal model of GFETs is developed combining both models as a tool for simulating the electrical behavior of graphene-based integrated circuits, dealing with the DC, transient behavior, and frequency response of the circuit. The drain current model is based in a drift-diffusion mechanism for the carrier transport coupled with an appropriate field-effect approach. The intrinsic capacitance model consists of a 16-capacitance matrix including self-capacitances and transcapacitances of a four-terminal GFET. To guarantee charge conservation, a Ward-Dutton linear charge partition scheme has been used. The large-signal model has been implemented in Verilog-A, being compatible with conventional circuit simulators and serving as a starting point toward the complete GFET device model that could incorporate additional non-idealities.

Large-Signal Model of Graphene Field-Effect Transistors -- Part I: Compact Modeling of GFET Intrinsic Capacitances

Abstract An electrical compact model for graphene FET device is proposed. Starting from Meric’s compact model, a trap model is introduced and the equivalent circuit is improved. We show that traps have an effect on the transconductance and influence consequently most figures of merit in circuit design. The model has been verified by comparison to DC and AC measurements versus bias and frequency on an advanced GFET having a transit frequency of about 10 GHz. Then, the compact model has been used to evaluate the transistor in a circuit context. A LNA has been designed and despite the poor voltage gain of the GFET, the LNA shows interesting performances when input and output matching of the circuit is performed. A power gain of |S21| = 4.2 dB is obtained, the reverse isolation is about |S12| = −10.6 dB, the Rollet stability factor K is 1.25 and the noise figure is 3.9 dB at 800 MHz.

Electrical compact modelling of graphene transistors

The present paper provides an accurate drift-diffusion model of the graphene field-effect transistor (GFET). A precise yet mathematically simple current-voltage relation is derived by focusing on device physics at energy levels close to the Dirac point. With respect to previous work, our approach extends modeling accuracy to the low-voltage biasing regime and improves the prediction of current saturation. These advantages are highlighted by a comparison study of the drain current, transconductance, output conductance, and intrinsic gain. The model has been implemented in Verilog-A and is compatible with conventional circuit simulators. It is provided as a tool for the exploration of GFET-based integrated circuit design. The model shows good agreement with measurement data from GFET prototypes.

An Accurate and Verilog-A Compatible Compact Model for Graphene Field-Effect Transistors

This paper provides a global overview of the radio-frequency (RF) performance potential of carbon-nanotube field-effect transistors (CNFET), which for the first time includes the impact of noise. We develop noise and manufacturing process variability extensions for the Stanford CNFET compact model, implemented in Verilog-A and compatible with conventional circuit simulators. CNFET figures-of-merit (FoM) are determined both on the device and on the circuit level. Compared to silicon technology, CNFET devices show much better performance in terms of most of the RF-CMOS requirements of the International Technology Roadmap for Semiconductors. FoM projections for basic RF building blocks (low-noise amplifier and oscillator) show that good performance can already be obtained with simple circuit topologies. The main advantage of CNFET circuits yet lies in easily reaching operation frequencies of several hundreds of gigahertz, which are hard to be exploited by silicon technologies at similar technology nodes.

Radio-Frequency Performance of Carbon Nanotube-Based Devices and Circuits Considering Noise and Process Variation

This work focuses on process variability and noise in carbon nanotube field-effect transistors (CNFET) to obtain a compact model usable for radiofrequency (RF) design and simulations. CNFET figures of merit (FoM) are determined and compared to International Technology Roadmap for Semiconductors (ITRS) requirements on conventional analog silicon-based devices. The developed model is also used to investigate on the impact of manufacturing process variability on the CNFET's RF-performance and noise behavior.

Carbon nanotube FET process variability and noise model for radiofrequency investigations

This paper focuses on the development of a compact noise model for radiofrequency (RF) carbon nanotube field-effect transistors (CNFET). The noise mechanisms in these devices are discussed and the impact of the different noise sources is analyzed. For the RF-CNFET under investigation a minimum noise figure NF min = 0.104 dB at 60 GHz is predicted. Our model is usable with conventional circuit simulators, which provides a basis for further investigations on CNFET-based RF building blocks.

Gerhard Martin Landauer

Papers

An Accurate and Verilog-A Compatible Compact Model for Graphene Field-Effect Transistors

Radio-Frequency Performance of Carbon Nanotube-Based Devices and Circuits Considering Noise and Process Variation

Carbon nanotube FET process variability and noise model for radiofrequency investigations

A compact noise model for carbon nanotube FETs