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An Accurate and Verilog-A Compatible Compact Model for Graphene Field-Effect Transistors

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TLDR
In this article, an accurate drift-diffusion model of GFETs is presented, which is based on device physics at energy levels close to the Dirac point, and is implemented in Verilog-A and is compatible with conventional circuit simulators.
Abstract
The present paper provides an accurate drift-diffusion model of the graphene field-effect transistor (GFET). A precise yet mathematically simple current-voltage relation is derived by focusing on device physics at energy levels close to the Dirac point. With respect to previous work, our approach extends modeling accuracy to the low-voltage biasing regime and improves the prediction of current saturation. These advantages are highlighted by a comparison study of the drain current, transconductance, output conductance, and intrinsic gain. The model has been implemented in Verilog-A and is compatible with conventional circuit simulators. It is provided as a tool for the exploration of GFET-based integrated circuit design. The model shows good agreement with measurement data from GFET prototypes.

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Citations
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Journal ArticleDOI

Graphene Field-Effect Transistor Model With Improved Carrier Mobility Analysis

TL;DR: In this paper, a SPICE-like graphene field effect transistor (GFET) model with an improved carrier mobility analysis is presented, which considers the mobility difference between the electrons and the holes in graphene, as well as the mobility variation against the carrier density.
Journal ArticleDOI

Large-Signal Model of Graphene Field-Effect Transistors -- Part I: Compact Modeling of GFET Intrinsic Capacitances

TL;DR: In this article, a circuit-compatible compact model of the intrinsic capacitances of graphene field-effect transistors (GFETs) is presented, together with a compact drain current model, and a large-signal model of GFETs is developed combining both models as a tool for simulating the electrical behavior of graphene-based integrated circuits.

Electrical compact modelling of graphene transistors

TL;DR: In this article, an electrical compact model for graphene FET device is proposed, where a trap model is introduced and the equivalent circuit is improved, and the model has been verified by comparison to DC and AC measurements versus bias and frequency on an advanced GFET having a transit frequency of about 10 GHz.
Journal ArticleDOI

Graphene Sensing Modulator: Toward Low-Noise, Self-Powered Wireless Microsensors

TL;DR: In this article, a self-powered, low-interference wireless sensor based on graphene circuits, which can have dual functions: chemical sensing at the molecular level and radio-frequency modulation, is presented.
Journal ArticleDOI

Understanding the bias dependence of low frequency noise in single layer graphene FETs

TL;DR: Channel regions nearby the source and drain terminals are found to dominate the total noise for gate biases close to the charge neutrality point (CNP), revealing for the first time the strong correlation between this gate dependence and the residual charge which is relevant in the vicinity of this specific bias point.
References
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Journal ArticleDOI

A roadmap for graphene

TL;DR: This work reviews recent progress in graphene research and in the development of production methods, and critically analyse the feasibility of various graphene applications.
Journal ArticleDOI

Current saturation in zero-bandgap, top-gated graphene field-effect transistors.

TL;DR: The first observation of saturating transistor characteristics in a graphene field-effect transistor is reported, demonstrating the feasibility of two-dimensional graphene devices for analogue and radio-frequency circuit applications without the need for bandgap engineering.
Journal ArticleDOI

Micrometer-Scale Ballistic Transport in Encapsulated Graphene at Room Temperature

TL;DR: The encapsulation makes graphene practically insusceptible to the ambient atmosphere and, simultaneously, allows the use of boron nitride as an ultrathin top gate dielectric.
Journal ArticleDOI

Wafer-Scale Graphene Integrated Circuit

TL;DR: A wafer-scale graphene circuit was demonstrated in which all circuit components, including graphene field-effect transistor and inductors, were monolithically integrated on a single silicon carbide wafer.
Journal ArticleDOI

A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part I: Model of the Intrinsic Channel Region

TL;DR: In this paper, a circuit-compatible compact model for the intrinsic channel region of the MOSFET-like single-walled carbon-nanotube field effect transistors (CNFETs) is presented.
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